From patchwork Tue Oct 17 17:40:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lalith Rajendran X-Patchwork-Id: 13425646 Received: from mail-ot1-f42.google.com (mail-ot1-f42.google.com [209.85.210.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE76A44469 for ; Tue, 17 Oct 2023 17:41:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jvrhg+h9" Received: by mail-ot1-f42.google.com with SMTP id 46e09a7af769-6c4bad60a1aso3597076a34.2 for ; Tue, 17 Oct 2023 10:41:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1697564509; x=1698169309; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=1Pn9eJVdwl+J/sFLPoMCtNv2U3ugpV05N/p/0aVkH1Y=; b=jvrhg+h94Z6llpqhRPmP6ShcS+I6hfDU18o7QI6r1INy5r3b3I+6WS/oQQtuw8P/Q9 doOv8L48PVUXPJBgXNz1dXPhVG03/KlK5dHIFfpZPt6Mfs514rF4vmATNOzn41R3CKZv aREZ2t/tFeJ6859QVIYP+svISHShGLLzZEr/I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697564509; x=1698169309; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1Pn9eJVdwl+J/sFLPoMCtNv2U3ugpV05N/p/0aVkH1Y=; b=jPb2kvIhcKRFe5rCM/w7+srD1VxKcxGw7n1orpmM07o7TnCwVFhpMQbiSU1SdBko0m 356gmjHsrsSNPi6NqywB0RcfQBNeqUNFrkzYAFP9+rTuBr+cvnLePCyOM/sNPrnduCS/ rw61PxNFeVILP6ys0d7Ob4xHkbBosf5vQe4TOvd3TFndVaRjQ7Urhfe1XwORqwxuQb3w ayqoo3P/x++ULakgUKXA8ZwKCz9/BPXcOA0N/ETxTMdz5WM+u+h9uYIXaIvhcQGE9A62 zeWRrjVmE4oTc5frIkN1hYzeYPqSkVX6A0xuQGR7XDgKdxHM92UK8YuOXlBe8MAbV2kD yg6A== X-Gm-Message-State: AOJu0Yw7sEUnTUZjZkb5oZ+mc5fcpZJKmHm/ZtAyzoU+rARpDxhYJZSY IAnDG+xl/ZQGvsr8KP5JwWL0fw== X-Google-Smtp-Source: AGHT+IGszE3Pnh4d2ZDJ8/XflC6nRCbUIzOSW0KfglBrRor01NS4jJl9PFXi4JjJsJqQSWvmhcOpGA== X-Received: by 2002:a05:6830:118b:b0:6b9:62f5:ac62 with SMTP id u11-20020a056830118b00b006b962f5ac62mr2715609otq.35.1697564508798; Tue, 17 Oct 2023 10:41:48 -0700 (PDT) Received: from lalithkraj-glaptop.corp.google.com ([2620:15c:2a:201:f4f7:57a:9a7d:3e2e]) by smtp.gmail.com with ESMTPSA id m16-20020a9d6090000000b006c20f55525esm339246otj.1.2023.10.17.10.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 10:41:48 -0700 (PDT) From: Lalith Rajendran To: LKML Cc: Lalith Rajendran , Benson Leung , Guenter Roeck , Tzung-Bi Shih , chrome-platform@lists.linux.dev Subject: [PATCH v1] FROMLIST: platform/chrome: cros_ec_lpc: Separate host command and irq disable Date: Tue, 17 Oct 2023 12:40:48 -0500 Message-ID: <20231017124047.1.Icc99145043c8d44142bb5ca64ea4c63a417c267b@changeid> X-Mailer: git-send-email 2.42.0.655.g421f12c284-goog Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Both cros host command and irq disable were moved to suspend prepare stage from late suspend recently. This is causing EC to report MKBP event timeouts during suspend stress testing. When the MKBP event timeouts happen during suspend, subsequent wakeup of AP by EC using MKBP doesn't happen properly. Although there are other issues to debug here, this change move the irq disabling part back to late suspend stage which is a general suggestion from the suspend kernel documentaiton to do irq disable as late as possible. Signed-off-by: Lalith Rajendran --- drivers/platform/chrome/cros_ec.c | 120 +++++++++++++++++++++----- drivers/platform/chrome/cros_ec.h | 4 + drivers/platform/chrome/cros_ec_lpc.c | 22 ++++- 3 files changed, 120 insertions(+), 26 deletions(-) diff --git a/drivers/platform/chrome/cros_ec.c b/drivers/platform/chrome/cros_ec.c index 5d36fbc75e1b..e18ee397bf0e 100644 --- a/drivers/platform/chrome/cros_ec.c +++ b/drivers/platform/chrome/cros_ec.c @@ -321,17 +321,8 @@ void cros_ec_unregister(struct cros_ec_device *ec_dev) EXPORT_SYMBOL(cros_ec_unregister); #ifdef CONFIG_PM_SLEEP -/** - * cros_ec_suspend() - Handle a suspend operation for the ChromeOS EC device. - * @ec_dev: Device to suspend. - * - * This can be called by drivers to handle a suspend event. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_suspend(struct cros_ec_device *ec_dev) +static int cros_ec_send_suspend_event(struct cros_ec_device *ec_dev) { - struct device *dev = ec_dev->dev; int ret; u8 sleep_event; @@ -343,7 +334,26 @@ int cros_ec_suspend(struct cros_ec_device *ec_dev) if (ret < 0) dev_dbg(ec_dev->dev, "Error %d sending suspend event to ec\n", ret); + return 0; +} +/** + * cros_ec_suspend_prepare() - Handle a suspend prepare operation for the ChromeOS EC device. + * @ec_dev: Device to suspend. + * + * This can be called by drivers to handle a suspend prepare stage of suspend. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_suspend_prepare(struct cros_ec_device *ec_dev) +{ + return cros_ec_send_suspend_event(ec_dev); +} +EXPORT_SYMBOL(cros_ec_suspend_prepare); + +static int cros_ec_disable_irq(struct cros_ec_device *ec_dev) +{ + struct device *dev = ec_dev->dev; if (device_may_wakeup(dev)) ec_dev->wake_enabled = !enable_irq_wake(ec_dev->irq); else @@ -354,6 +364,35 @@ int cros_ec_suspend(struct cros_ec_device *ec_dev) return 0; } + +/** + * cros_ec_suspend_late() - Handle a suspend late operation for the ChromeOS EC device. + * @ec_dev: Device to suspend. + * + * This can be called by drivers to handle a suspend late stage of suspend. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_suspend_late(struct cros_ec_device *ec_dev) +{ + return cros_ec_disable_irq(ec_dev); +} +EXPORT_SYMBOL(cros_ec_suspend_late); + +/** + * cros_ec_suspend() - Handle a suspend operation for the ChromeOS EC device. + * @ec_dev: Device to suspend. + * + * This can be called by drivers to handle a suspend event. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_suspend(struct cros_ec_device *ec_dev) +{ + cros_ec_send_suspend_event(ec_dev); + cros_ec_disable_irq(ec_dev); + return 0; +} EXPORT_SYMBOL(cros_ec_suspend); static void cros_ec_report_events_during_suspend(struct cros_ec_device *ec_dev) @@ -370,22 +409,11 @@ static void cros_ec_report_events_during_suspend(struct cros_ec_device *ec_dev) } } -/** - * cros_ec_resume() - Handle a resume operation for the ChromeOS EC device. - * @ec_dev: Device to resume. - * - * This can be called by drivers to handle a resume event. - * - * Return: 0 on success or negative error code. - */ -int cros_ec_resume(struct cros_ec_device *ec_dev) +static int cros_ec_send_resume_event(struct cros_ec_device *ec_dev) { int ret; u8 sleep_event; - ec_dev->suspended = false; - enable_irq(ec_dev->irq); - sleep_event = (!IS_ENABLED(CONFIG_ACPI) || pm_suspend_via_firmware()) ? HOST_SLEEP_EVENT_S3_RESUME : HOST_SLEEP_EVENT_S0IX_RESUME; @@ -394,6 +422,25 @@ int cros_ec_resume(struct cros_ec_device *ec_dev) if (ret < 0) dev_dbg(ec_dev->dev, "Error %d sending resume event to ec\n", ret); + return 0; +} + +/** + * cros_ec_resume_complete() - Handle a resume complete operation for the ChromeOS EC device. + * @ec_dev: Device to resume. + * + * This can be called by drivers to handle a resume complete stage of resume. + */ +void cros_ec_resume_complete(struct cros_ec_device *ec_dev) +{ + cros_ec_send_resume_event(ec_dev); +} +EXPORT_SYMBOL(cros_ec_resume_complete); + +static int cros_ec_enable_irq(struct cros_ec_device *ec_dev) +{ + ec_dev->suspended = false; + enable_irq(ec_dev->irq); if (ec_dev->wake_enabled) disable_irq_wake(ec_dev->irq); @@ -407,6 +454,35 @@ int cros_ec_resume(struct cros_ec_device *ec_dev) return 0; } + +/** + * cros_ec_resume_early() - Handle a resume early operation for the ChromeOS EC device. + * @ec_dev: Device to resume. + * + * This can be called by drivers to handle a resume early stage of resume. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_resume_early(struct cros_ec_device *ec_dev) +{ + return cros_ec_enable_irq(ec_dev); +} +EXPORT_SYMBOL(cros_ec_resume_early); + +/** + * cros_ec_resume() - Handle a resume operation for the ChromeOS EC device. + * @ec_dev: Device to resume. + * + * This can be called by drivers to handle a resume event. + * + * Return: 0 on success or negative error code. + */ +int cros_ec_resume(struct cros_ec_device *ec_dev) +{ + cros_ec_enable_irq(ec_dev); + cros_ec_send_resume_event(ec_dev); + return 0; +} EXPORT_SYMBOL(cros_ec_resume); #endif diff --git a/drivers/platform/chrome/cros_ec.h b/drivers/platform/chrome/cros_ec.h index bbca0096868a..566332f48789 100644 --- a/drivers/platform/chrome/cros_ec.h +++ b/drivers/platform/chrome/cros_ec.h @@ -14,7 +14,11 @@ int cros_ec_register(struct cros_ec_device *ec_dev); void cros_ec_unregister(struct cros_ec_device *ec_dev); int cros_ec_suspend(struct cros_ec_device *ec_dev); +int cros_ec_suspend_late(struct cros_ec_device *ec_dev); +int cros_ec_suspend_prepare(struct cros_ec_device *ec_dev); int cros_ec_resume(struct cros_ec_device *ec_dev); +int cros_ec_resume_early(struct cros_ec_device *ec_dev); +void cros_ec_resume_complete(struct cros_ec_device *ec_dev); irqreturn_t cros_ec_irq_thread(int irq, void *data); diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 9083a7d58d53..ed498278a223 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -560,22 +560,36 @@ MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table); static int cros_ec_lpc_prepare(struct device *dev) { struct cros_ec_device *ec_dev = dev_get_drvdata(dev); - - return cros_ec_suspend(ec_dev); + return cros_ec_suspend_prepare(ec_dev); } static void cros_ec_lpc_complete(struct device *dev) { struct cros_ec_device *ec_dev = dev_get_drvdata(dev); - cros_ec_resume(ec_dev); + cros_ec_resume_complete(ec_dev); +} + +static int cros_ec_lpc_suspend_late(struct device *dev) +{ + struct cros_ec_device *ec_dev = dev_get_drvdata(dev); + + return cros_ec_suspend_late(ec_dev); +} + +static int cros_ec_lpc_resume_early(struct device *dev) +{ + struct cros_ec_device *ec_dev = dev_get_drvdata(dev); + + return cros_ec_resume_early(ec_dev); } #endif static const struct dev_pm_ops cros_ec_lpc_pm_ops = { #ifdef CONFIG_PM_SLEEP .prepare = cros_ec_lpc_prepare, - .complete = cros_ec_lpc_complete + .complete = cros_ec_lpc_complete, #endif + SET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend_late, cros_ec_lpc_resume_early) }; static struct platform_driver cros_ec_lpc_driver = {