[5.10.y-cip,00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK

Message ID	20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK Date: Thu, 16 Dec 2021 12:54:22 +0000 Message-Id: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Series	Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK \| expand [5.10.y-cip,00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK [5.10.y-cip,01/24] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings [5.10.y-cip,02/24] serial: sh-sci: Add support for RZ/G2L SoC [5.10.y-cip,03/24] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver [5.10.y-cip,04/24] dt-bindings: clock: Add r9a07g044 CPG Clock Definitions [5.10.y-cip,05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC [5.10.y-cip,06/24] clk: renesas: Add support for R9A07G044 SoC [5.10.y-cip,07/24] clk: renesas: r9a07g044: Rename divider table [5.10.y-cip,08/24] clk: renesas: r9a07g044: Fix P1 Clock [5.10.y-cip,09/24] clk: renesas: r9a07g044: Add P2 Clock support [5.10.y-cip,10/24] clk: renesas: rzg2l: Add multi clock PM support [5.10.y-cip,11/24] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's [5.10.y-cip,12/24] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK [5.10.y-cip,13/24] arm64: dts: renesas: r9a07g044: Add SYSC node [5.10.y-cip,14/24] dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions [5.10.y-cip,15/24] clk: renesas: rzg2l: Remove unneeded semicolon [5.10.y-cip,16/24] clk: renesas: rzg2l: Fix return value and unused assignment [5.10.y-cip,17/24] clk: renesas: rzg2l: Fix a double free on error [5.10.y-cip,18/24] clk: renesas: rzg2l: Avoid mixing error pointers and NULL [5.10.y-cip,19/24] clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() [5.10.y-cip,20/24] clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] [5.10.y-cip,21/24] clk: mux: provide devm_clk_hw_register_mux() [5.10.y-cip,22/24] clk: renesas: rzg2l: Add support to handle MUX clocks [5.10.y-cip,23/24] clk: renesas: rzg2l: Add support to handle coupled clocks [5.10.y-cip,24/24] clk: renesas: rzg2l: Fix clk status function

Message ID

20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)

Headers

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L
 SoC + SMARC EVK
Date: Thu, 16 Dec 2021 12:54:22 +0000
Message-Id: <20211216125446.15451-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Series

Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK | expand

Message

Lad Prabhakar Dec. 16, 2021, 12:54 p.m. UTC

Hi All,

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
  - CPU
  - CPG
  - GIC
* Initial device tree for RZ/G2L SMARC EVK
  - memory
  - External input clock
  - SCIF

All the patches have been cherry picked from 5.16-rc5. For testing purpose
MR [0] can be used.

[0] https://gitlab.com/cip-project/cip-kernel/
cip-kernel-config/-/merge_requests/52

Cheers,
Prabhakar

Biju Das (9):
  serial: sh-sci: Add support for RZ/G2L SoC
  clk: renesas: r9a07g044: Rename divider table
  clk: renesas: r9a07g044: Fix P1 Clock
  clk: renesas: r9a07g044: Add P2 Clock support
  clk: renesas: rzg2l: Add multi clock PM support
  dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions
  clk: renesas: rzg2l: Add support to handle MUX clocks
  clk: renesas: rzg2l: Add support to handle coupled clocks
  clk: renesas: rzg2l: Fix clk status function

Dan Carpenter (2):
  clk: renesas: rzg2l: Fix a double free on error
  clk: renesas: rzg2l: Avoid mixing error pointers and NULL

Dmitry Baryshkov (1):
  clk: mux: provide devm_clk_hw_register_mux()

Geert Uytterhoeven (1):
  clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]

Lad Prabhakar (9):
  dt-bindings: serial: renesas,scif: Document r9a07g044 bindings
  dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
  dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
  clk: renesas: Add CPG core wrapper for RZ/G2L SoC
  clk: renesas: Add support for R9A07G044 SoC
  arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's
  arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
  arm64: dts: renesas: r9a07g044: Add SYSC node
  clk: renesas: rzg2l: Fix off-by-one check in
    rzg2l_cpg_clk_src_twocell_get()

Yang Li (2):
  clk: renesas: rzg2l: Remove unneeded semicolon
  clk: renesas: rzg2l: Fix return value and unused assignment

 .../bindings/clock/renesas,rzg2l-cpg.yaml     |  83 ++
 .../bindings/serial/renesas,scif.yaml         |   4 +
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    | 132 +++
 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi  |  25 +
 .../boot/dts/renesas/r9a07g044l2-smarc.dts    |  21 +
 arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi  |  13 +
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  |  27 +
 drivers/clk/clk-mux.c                         |  35 +
 drivers/clk/renesas/Kconfig                   |   9 +
 drivers/clk/renesas/Makefile                  |   2 +
 drivers/clk/renesas/r9a07g044-cpg.c           | 142 +++
 drivers/clk/renesas/rzg2l-cpg.c               | 844 ++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.h               | 176 ++++
 drivers/tty/serial/sh-sci.c                   |  12 +-
 drivers/tty/serial/sh-sci.h                   |   1 +
 include/dt-bindings/clock/r9a07g044-cpg.h     | 219 +++++
 include/linux/clk-provider.h                  |  13 +
 18 files changed, 1759 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
 create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c
 create mode 100644 drivers/clk/renesas/rzg2l-cpg.c
 create mode 100644 drivers/clk/renesas/rzg2l-cpg.h
 create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h

Comments

Nobuhiro Iwamatsu Dec. 17, 2021, 7:42 a.m. UTC | #1

Hi Prabhakar,

> This patch series adds the following:
> * Serial support
> * Clock support
> * Initial RZ/G2L SoC DTSI
>   - CPU
>   - CPG
>   - GIC
> * Initial device tree for RZ/G2L SMARC EVK
>   - memory
>   - External input clock
>   - SCIF
>
> All the patches have been cherry picked from 5.16-rc5. For testing purpose
> MR [0] can be used.

I will check this series, and I am also checking the build.
  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/431663140

Best regards,
  Nobuhiro

Pavel Machek Dec. 17, 2021, 10:39 a.m. UTC | #2

Hi!

> > This patch series adds the following:
> > * Serial support
> > * Clock support
> > * Initial RZ/G2L SoC DTSI
> >   - CPU
> >   - CPG
> >   - GIC
> > * Initial device tree for RZ/G2L SMARC EVK
> >   - memory
> >   - External input clock
> >   - SCIF
> >
> > All the patches have been cherry picked from 5.16-rc5. For testing purpose
> > MR [0] can be used.
> 
> I will check this series, and I am also checking the build.
>
> > https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/431663140

Thank you. I checked the series and only found some details (some of
them were fixed later in the series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@denx.de>
								Pavel