| Message ID | 20240130203346.94488-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for Renesas RZ/Five RISC-V SoC | expand |
Hi! > This patch series aims to add support for Renesas RZ/Five RISC-V SoC, > support for this SoC has already been added to 6.1-cip kernel. > > Sending this series as an RFC as, > 1] Support for Global DMA cohernet pool is added > 2] As support for non-coherent DMA is missing for RISC-V core, > required changes have been added directly in ax45mp_cache.c > (ie patch #26) > 3] Patch #26 has been newly added, rest of the patches have been > cherry-picked from upstream kernel. I quickly went through this, and found nothing too crazy. But as this adds whole new architecture into 5.10-cip, I guess I should get confirmation on the IRC. We'll also need to add this (and RISC-V qemu) to 5.10 testing. Best regards, Pavel
Hello Pavel, > From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On > Behalf Of Pavel Machek via lists.cip-project.org > Sent: Wednesday, January 31, 2024 11:34 AM > > Hi! > > > This patch series aims to add support for Renesas RZ/Five RISC-V SoC, > > support for this SoC has already been added to 6.1-cip kernel. > > > > Sending this series as an RFC as, > > 1] Support for Global DMA cohernet pool is added > > 2] As support for non-coherent DMA is missing for RISC-V core, > > required changes have been added directly in ax45mp_cache.c > > (ie patch #26) > > 3] Patch #26 has been newly added, rest of the patches have been > > cherry-picked from upstream kernel. > > I quickly went through this, and found nothing too crazy. But as this > adds whole new architecture into 5.10-cip, I guess I should get My understanding is that CIP is already supporting RSIC-V in 5.10-cip, as qemu riscv64 is listed as a reference platform for it [0]. [0] https://wiki.linuxfoundation.org/civilinfrastructureplatform/ciptesting/cipreferencehardware > confirmation on the IRC. We'll also need to add this (and RISC-V qemu) > to 5.10 testing. I've done a test run for build&boot testing for RZ/Five [1] based on this MR and it's dependencies, using a defconfig [2] provided by Prabhakar. If accepted I'll add support to the official CIP pipelines. [1] https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1160504705 [2] https://gitlab.com/cip-project/cip-kernel/linux-cip/-/commit/c597a7df976d7dbbfe82d8de26e75c1f78c94f24 Kind regards, Chris
Hi Pavel, > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: Wednesday, January 31, 2024 11:34 AM > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [RFC PATCH 5.10.y-cip 00/39] Add support for Renesas RZ/Five RISC-V SoC > > Hi! > > > This patch series aims to add support for Renesas RZ/Five RISC-V SoC, > > support for this SoC has already been added to 6.1-cip kernel. > > > > Sending this series as an RFC as, > > 1] Support for Global DMA cohernet pool is added 2] As support for > > non-coherent DMA is missing for RISC-V core, > > required changes have been added directly in ax45mp_cache.c > > (ie patch #26) > > 3] Patch #26 has been newly added, rest of the patches have been > > cherry-picked from upstream kernel. > > I quickly went through this, and found nothing too crazy. But as this adds whole new architecture into > 5.10-cip, I guess I should get confirmation on the IRC. We'll also need to add this (and RISC-V qemu) > to 5.10 testing. > Now that we have agreed for RISC-V support on 5.10-cip, shall I send non RFC series? Cheers, Prabhakar > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Hi! > > > This patch series aims to add support for Renesas RZ/Five RISC-V SoC, > > > support for this SoC has already been added to 6.1-cip kernel. > > > > > > Sending this series as an RFC as, > > > 1] Support for Global DMA cohernet pool is added 2] As support for > > > non-coherent DMA is missing for RISC-V core, > > > required changes have been added directly in ax45mp_cache.c > > > (ie patch #26) > > > 3] Patch #26 has been newly added, rest of the patches have been > > > cherry-picked from upstream kernel. > > > > I quickly went through this, and found nothing too crazy. But as this adds whole new architecture into > > 5.10-cip, I guess I should get confirmation on the IRC. We'll also need to add this (and RISC-V qemu) > > to 5.10 testing. > > > Now that we have agreed for RISC-V support on 5.10-cip, shall I send non RFC series? It will be same as RFC series, right? :-). So I guess no need to do that, I believe we can just review and apply this one. Best regards, Pavel
Hi Pavel, > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: Monday, February 5, 2024 10:15 AM > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: Pavel Machek <pavel@denx.de>; cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu > <nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [RFC PATCH 5.10.y-cip 00/39] Add support for Renesas RZ/Five RISC-V SoC > > Hi! > > > > > This patch series aims to add support for Renesas RZ/Five RISC-V > > > > SoC, support for this SoC has already been added to 6.1-cip kernel. > > > > > > > > Sending this series as an RFC as, > > > > 1] Support for Global DMA cohernet pool is added 2] As support for > > > > non-coherent DMA is missing for RISC-V core, > > > > required changes have been added directly in ax45mp_cache.c > > > > (ie patch #26) > > > > 3] Patch #26 has been newly added, rest of the patches have been > > > > cherry-picked from upstream kernel. > > > > > > I quickly went through this, and found nothing too crazy. But as > > > this adds whole new architecture into 5.10-cip, I guess I should get > > > confirmation on the IRC. We'll also need to add this (and RISC-V qemu) to 5.10 testing. > > > > > Now that we have agreed for RISC-V support on 5.10-cip, shall I send non RFC series? > > It will be same as RFC series, right? :-). So I guess no need to do that, I believe we can just review > and apply this one. > There is one small change in patch #26 (keeping changes identical to upstream) and rest remains unchanged. Cheers, Prabhakar
Hi! > > > > > This patch series aims to add support for Renesas RZ/Five RISC-V > > > > > SoC, support for this SoC has already been added to 6.1-cip kernel. > > > > > > > > > > Sending this series as an RFC as, > > > > > 1] Support for Global DMA cohernet pool is added 2] As support for > > > > > non-coherent DMA is missing for RISC-V core, > > > > > required changes have been added directly in ax45mp_cache.c > > > > > (ie patch #26) > > > > > 3] Patch #26 has been newly added, rest of the patches have been > > > > > cherry-picked from upstream kernel. > > > > > > > > I quickly went through this, and found nothing too crazy. But as > > > > this adds whole new architecture into 5.10-cip, I guess I should get > > > > confirmation on the IRC. We'll also need to add this (and RISC-V qemu) to 5.10 testing. > > > > > > > Now that we have agreed for RISC-V support on 5.10-cip, shall I send non RFC series? > > > > It will be same as RFC series, right? :-). So I guess no need to do that, I believe we can just review > > and apply this one. > > > There is one small change in patch #26 (keeping changes identical to upstream) and rest remains unchanged. Okay, so let's regenerate the series, and prepend the patches from the preparatory series as I did not apply them. Thanks and best regards, Pavel
Hi Pavel, > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: Monday, February 5, 2024 10:29 AM > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: Pavel Machek <pavel@denx.de>; cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu > <nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [RFC PATCH 5.10.y-cip 00/39] Add support for Renesas RZ/Five RISC-V SoC > > Hi! > > > > > > This patch series aims to add support for Renesas RZ/Five > > > > > > RISC-V SoC, support for this SoC has already been added to 6.1-cip kernel. > > > > > > > > > > > > Sending this series as an RFC as, 1] Support for Global DMA > > > > > > cohernet pool is added 2] As support for non-coherent DMA is > > > > > > missing for RISC-V core, > > > > > > required changes have been added directly in ax45mp_cache.c > > > > > > (ie patch #26) > > > > > > 3] Patch #26 has been newly added, rest of the patches have been > > > > > > cherry-picked from upstream kernel. > > > > > > > > > > I quickly went through this, and found nothing too crazy. But as > > > > > this adds whole new architecture into 5.10-cip, I guess I should > > > > > get confirmation on the IRC. We'll also need to add this (and RISC-V qemu) to 5.10 testing. > > > > > > > > > Now that we have agreed for RISC-V support on 5.10-cip, shall I send non RFC series? > > > > > > It will be same as RFC series, right? :-). So I guess no need to do > > > that, I believe we can just review and apply this one. > > > > > There is one small change in patch #26 (keeping changes identical to upstream) and rest remains > unchanged. > > Okay, so let's regenerate the series, and prepend the patches from the preparatory series as I did not > apply them. > Sure will do that now. Cheers, Prabhakar > Thanks and best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Hi All, This patch series aims to add support for Renesas RZ/Five RISC-V SoC, support for this SoC has already been added to 6.1-cip kernel. Sending this series as an RFC as, 1] Support for Global DMA cohernet pool is added 2] As support for non-coherent DMA is missing for RISC-V core, required changes have been added directly in ax45mp_cache.c (ie patch #26) 3] Patch #26 has been newly added, rest of the patches have been cherry-picked from upstream kernel. Note, - This patch series applies on top of series [0]. [0] https://patchwork.kernel.org/project/cip-dev/cover/20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Christoph Hellwig (5): dma-direct: add support for dma_coherent_default_memory dma-mapping: allow using the global coherent pool for !ARM dma-mapping: simplify dma_init_coherent_memory dma-mapping: add a dma_init_global_coherent helper dma-mapping: make the global coherent pool conditional Conor Dooley (1): riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Heiko Stuebner (1): of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar (25): riscv: Kconfig: Enable cpufreq kconfig menu irqchip/sifive-plic: Add support for Renesas RZ/Five SoC clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS dt-bindings: riscv: Sort the CPU core list alphabetically dt-bindings: riscv: Add Andes AX45MP core to the list dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller soc: renesas: Identify RZ/Five SoC clk: renesas: r9a07g043: Add support for RZ/Five SoC cache: Add L2 cache management for Andes AX45MP RISC-V core cache: ax45mp_cache: Add non coherent support soc: renesas: Kconfig: Select the required configs for RZ/Five SoC riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C riscv: dts: renesas: rzfive-smarc-som: Enable WDT riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} riscv: dts: renesas: r9a07g043f: Add L2 cache node riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Niklas Cassel (2): irqchip/sifive-plic: Improve naming scheme for per context offsets irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Samuel Holland (4): of/irq: Use interrupts-extended to find parent irqchip/sifive-plic: Make better use of the effective affinity mask irqchip/sifive-plic: Separate the enable and mask operations clocksource/drivers/riscv: Increase the clock source rating Xiongfeng Wang (1): cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() .../cache/andestech,ax45mp-cache.yaml | 81 +++++++ .../devicetree/bindings/riscv/cpus.yaml | 7 +- MAINTAINERS | 7 + arch/riscv/Kconfig | 3 +- arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 72 ++++++ .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 24 ++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 8 + arch/riscv/kernel/time.c | 9 - drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/base/cacheinfo.c | 1 + drivers/cache/Kconfig | 12 + drivers/cache/Makefile | 3 + drivers/cache/ax45mp_cache.c | 222 ++++++++++++++++++ drivers/clk/renesas/r9a07g043-cpg.c | 32 +++ drivers/clocksource/renesas-ostm.c | 2 +- drivers/clocksource/timer-riscv.c | 7 +- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 178 ++++++++++---- drivers/mmc/host/Kconfig | 4 +- drivers/of/address.c | 17 +- drivers/of/irq.c | 13 +- drivers/soc/renesas/Kconfig | 12 + drivers/soc/renesas/renesas-soc.c | 13 + include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++ include/linux/dma-map-ops.h | 18 +- kernel/dma/Kconfig | 4 + kernel/dma/coherent.c | 161 ++++++------- kernel/dma/direct.c | 17 ++ 33 files changed, 822 insertions(+), 164 deletions(-) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/ax45mp_cache.c