| Message ID | 20240724091240.67115-1-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Revert "Add missing cache-level properties" | expand |
Hi! > The patch series revert the commit f703a1ddec6a ("arm64: dts: renesas: > rzg2l: Add missing cache-level properties") as it is triggering a warning > on linux-6.1.y-cip "cacheinfo: Unable to detect cache hierarchy for CPU 0" > > The the proper fix needs backporting generic/architecture-specific changes > to support the "cache-level" in device tree. > > Mainline patch[1]-[5] fixes the warning message, but there is drop in > ethernet rx performance on RZ/G2L SoCs and also triggers another warning > message "Early cacheinfo failed, ret = -2" on RZ/G2{H,M,N,E} family > > patch [6]->[9] fixes the above warning message. Still we left out with > ethernet rx performance on RZ/G2L SoCs, which needs backporting further > patches. > Since [1]->[9] impacts all architectures, it is better not to backport > these patches on linux-6.1.y-cip. Ok, this looks like reasonable solution. I can apply it if it passes testing and there are no other comments. Best regards, Pavel
HI all, > -----Original Message----- > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: Wednesday, July 24, 2024 6:13 PM > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□ > ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de> > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> > Subject: [PATCH 6.1.y-cip 0/1] Revert "Add missing cache-level properties" > > The patch series revert the commit f703a1ddec6a ("arm64: dts: renesas: > rzg2l: Add missing cache-level properties") as it is triggering a warning on > linux-6.1.y-cip "cacheinfo: Unable to detect cache hierarchy for CPU 0" > > The the proper fix needs backporting generic/architecture-specific changes to > support the "cache-level" in device tree. > > Mainline patch[1]-[5] fixes the warning message, but there is drop in ethernet > rx performance on RZ/G2L SoCs and also triggers another warning message > "Early cacheinfo failed, ret = -2" on RZ/G2{H,M,N,E} family > > patch [6]->[9] fixes the above warning message. Still we left out with > ethernet rx performance on RZ/G2L SoCs, which needs backporting further > patches. > Since [1]->[9] impacts all architectures, it is better not to backport these > patches on linux-6.1.y-cip. > > [1] commit c3719bd9 ("cacheinfo: Use RISC-V's init_cache_level() as generic > OF implementation") [2] commit fa4d566a ("ACPI: PPTT: Remove > acpi_find_cache_levels()") [3] commit bd500361 ("ACPI: PPTT: Update > acpi_find_last_cache_level() to acpi_get_cache_info()") [4] commit > 5944ce09("arch_topology: Build cacheinfo from primary CPU") [5] commit > 6a249151 ("Revert "riscv: Set more data to cacheinfo"") [6] commit 3da72e18 > ("cacheinfo: Decrement refcount in cache_setup_of_node()") [7] commit > ecaef469 ("cacheinfo: Initialize variables in fetch_cache_info()") [8] commit > c931680c("cacheinfo: Add arm64 early level initializer implementation") [9] > commit 6539cffa("cacheinfo: Add arch specific early level initializer") > > Biju Das (1): > Revert "arm64: dts: renesas: rzg2l: Add missing cache-level > properties" > > arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 1 - > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 - > arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 - > 3 files changed, 3 deletions(-) OK, I ack this revert patch. Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Best regards, Nobuhiro
The patch series revert the commit f703a1ddec6a ("arm64: dts: renesas: rzg2l: Add missing cache-level properties") as it is triggering a warning on linux-6.1.y-cip "cacheinfo: Unable to detect cache hierarchy for CPU 0" The the proper fix needs backporting generic/architecture-specific changes to support the "cache-level" in device tree. Mainline patch[1]-[5] fixes the warning message, but there is drop in ethernet rx performance on RZ/G2L SoCs and also triggers another warning message "Early cacheinfo failed, ret = -2" on RZ/G2{H,M,N,E} family patch [6]->[9] fixes the above warning message. Still we left out with ethernet rx performance on RZ/G2L SoCs, which needs backporting further patches. Since [1]->[9] impacts all architectures, it is better not to backport these patches on linux-6.1.y-cip. [1] commit c3719bd9 ("cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation") [2] commit fa4d566a ("ACPI: PPTT: Remove acpi_find_cache_levels()") [3] commit bd500361 ("ACPI: PPTT: Update acpi_find_last_cache_level() to acpi_get_cache_info()") [4] commit 5944ce09("arch_topology: Build cacheinfo from primary CPU") [5] commit 6a249151 ("Revert "riscv: Set more data to cacheinfo"") [6] commit 3da72e18 ("cacheinfo: Decrement refcount in cache_setup_of_node()") [7] commit ecaef469 ("cacheinfo: Initialize variables in fetch_cache_info()") [8] commit c931680c("cacheinfo: Add arm64 early level initializer implementation") [9] commit 6539cffa("cacheinfo: Add arch specific early level initializer") Biju Das (1): Revert "arm64: dts: renesas: rzg2l: Add missing cache-level properties" arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 1 - arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 - arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 - 3 files changed, 3 deletions(-)