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Wed, 12 Mar 2025 11:23:38 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Date: Wed, 12 Mar 2025 12:21:37 +0100 Message-ID: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 X-ClientProxiedBy: FR4P281CA0246.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:f5::15) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|TY3PR01MB10581:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e23467d-499a-4651-b0b7-08dd615855b2 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|376014|366016|1800799024|38350700014; X-Microsoft-Antispam-Message-Info: XtRduFZQiS5APFHdNUfQJtrR2uhGHKoQ3R8ilRgpxStqsX2+o+pAjnbr1gDNl5mjLLdEarEfsYUybdLqfw2esKX+vEcxsqd9zgUqcM46nKw5LrO0bwS/yRpFF9VfRyIu1Vvf5bf429vBywp1/2Vkn0Vn7Cak44NHCZMtiQREzdRsXKIODEx/rGwF4+FfhgaRBJwaBRLryAvy/ox6d8nvXe1u1eqAUHp1j7ECLkYq+YlHyw0IiW2UWZ/zdHc+rtkymX0rddRYkajYEC28v2Qj5Fc5B/QaZv6Eor/sxZ+QtKIt7IB1KzPi1ogDS44OHTi8BSN7Ydf6egDYXvxZ6palWyDDSLbf4zDNi/ksao4+Z1QNGteUrOm4d0bMACYSdrpU5faLKkjsxDi/bDvtKm5FT2g+2Jvmz53B0ts5W3mtBYo77ePj3DSyBq17JaDIZUEXVs5CV4VP/eMCEuC/fiBQOS+YHYooOyjL/T1Y7BpqCrxYYwo/E4/KbD7ZurZvmfvm+J6UbK6NESSQolEGWRhSNOpWCzcmGMo3xsOOsNQ22qk4ZPFTsSGfS1VUhbRlIZpgCj9m43YSc+HkuuXqw3OZhXk1l17tNCEO11mhSyXkkM62xn3IEbbZspQF6b4ijA9LQItQB2DGj6keyadQLQLn0CzaQ5Tv4gxnb/NfcbeXN5d7MfN3/LGARZLuqJN4r524qA9mhBR/SO/8TP2t6pgWmNH3/GusOZq2Vxjfyd9JUf8u5S27z7EAcDj66DSM8yTrCH0+0CME9XNwDd/QYhFNozQ89FvH1dIARVwPwd8v6vLFUp0m53yAdPKCSAf3hqiU0XT5IRgKZ3IZlM6yxpfc5n2kRc8b9JB1758D4qR3PekUilKGZi7OYPh7RYoIodf5pcTeZaPXd9E9vLjQQi0y73QMjJpzS3zkfH2jPDHbuT1FF8hHnpI/doxWyr9b5jnc17WimTSlerSfpKwbgtXSJfwF9R32EBIQLUdzXkg3f97l3xgdnJoDehq5mCHQ1nlMV+RxwLKTQa1kXM5Q39kccFSoMxCkbTXra3bPz8U8tMt+rMgpQPeMzM0nJBpSaidMo/Rh3z5YdjwDYyDTAxBUtCt1cnsQKl0X3BEder85ITZL0S6s6QkU+FzSzzYMn0hhvCVAIZYqruCzsJE9jOTnlua9+cq/2lgZ4+w8bnDCvi5zM8UNegjYUXeP1nDFsSd2Q9/B3CF8CkG972jquXKy4hPEDSOML7N90cSuQbP6teLwmuCQEMGhhUA9o106JQn+awmNlt8GDlzQkmn6ajun4wiOAgcZHJ4V+QNFpv7aTeemgqUflXvIgcoIXhSVAy8qzDvs8U062BOGubnCG/x6EVZI9yyWPXdRvvuNh2H5NL/EHMqsjMB0jcYki6czyuVFsZ9HPG3661UP1gGFgm0b7U+TNAMD71vLEdsgx95t3jV3byb63IDlgwXOxFQ02BXp X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:OS9PR01MB13950.jpnprd01.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(52116014)(376014)(366016)(1800799024)(38350700014);DIR:OUT;SFP:1101; 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Thu, 13 Mar 2025 01:32:15 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18092 Dear All, This series add support for RZ/G3E SoC to linux-6.1.y-cip kernel. All patches are cherry-picked from mainline kernel. base commit: 8da62141b20b (tag: v6.1.129-cip38, linux-cip/linux-6.1.y-cip) Thanks & Regards, Tommaso Andy Shevchenko (1): pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API Biju Das (24): dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: clock: renesas: Document RZ/G3E SoC CPG clk: renesas: rzv2h: Add MSTOP support clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: r9a09g047: Add I2C clocks/resets arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board soc: renesas: Add RZ/G3E (R9A09G047) config option arm64: defconfig: Enable R9A09G047 SoC dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H dt-bindings: pinctrl: renesas: Document RZ/G3E SoC pinctrl: renesas: rzg2l: Use dev_err_probe() pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add pincontrol node dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol dt-bindings: i2c: renesas,riic: Document the R9A09G047 support arm64: dts: renesas: r9a09g047: Add I2C nodes Claudiu Beznea (5): serial: sh-sci: Check if TX data was written to device in .tx_empty() serial: sh-sci: Move runtime PM enable to sci_probe_single() serial: sh-sci: Clean sci_ports[0] after at earlycon exit serial: sh-sci: Increment the runtime usage counter for the earlycon device dt-bindings: i2c: renesas,riic: Document the R9A08G045 support Fabrizio Castro (2): clk: renesas: r9a09g057: Add clock and reset entries for ICU pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX Geert Uytterhoeven (1): serial: sh-sci: Use plain struct copy in early_console_setup() Kartik (1): mm/util: Introduce kmemdup_array() Lad Prabhakar (46): dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: Add family-specific clock driver for RZ/V2H(P) clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties pinctrl: renesas: rzg2l: Allow more bits for pin configuration pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg pinctrl: renesas: rzg2l: Enable variable configuration for all pinctrl: renesas: rzg2l: Validate power registers for SD and ETH pinctrl: renesas: rzg2l: Add function pointer for PFC register locking pinctrl: renesas: rzg2l: Add function pointer for PMC register write pinctrl: renesas: rzg2l: Add function pointers for OEN register access pinctrl: renesas: rzg2l: Add support to configure slew-rate pinctrl: renesas: rzg2l: Add support for pull-up/down pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_config() pinctrl: renesas: rzg2l: Add support for custom parameters pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file pinctrl: renesas: rzg2l: Reorganize variable configuration macro pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support PIN_CFG_OEN pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names' dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as required dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF support serial: sh-sci: Add support for RZ/V2H(P) SoC dt-bindings: i2c: renesas,riic: Document RZ/Five SoC dt-bindings: i2c: renesas,riic: Document R9A09G057 support i2c: riic: Introduce helper functions for I2C read/write operations i2c: riic: Pass register offsets and chip details as OF data i2c: riic: Add support for R9A09G057 SoC Paul Barker (3): pinctrl: renesas: rzg2l: Clarify OEN read/write support pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions pinctrl: renesas: rzg2l: Support output enable on RZ/G2L Shen Lichuan (1): pinctrl: renesas: Switch to use kmemdup_array() Wolfram Sang (1): serial: sh-sci: describe locking requirements for invalidating RXDMA .../devicetree/bindings/arm/renesas.yaml | 17 + .../bindings/clock/renesas,rzv2h-cpg.yaml | 83 ++ .../devicetree/bindings/i2c/renesas,riic.yaml | 26 +- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 61 +- .../bindings/serial/renesas,scif.yaml | 141 +- arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 387 ++++++ arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 + .../boot/dts/renesas/r9a09g047e57-smarc.dts | 31 + arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 + .../boot/dts/renesas/renesas-smarc2.dtsi | 24 + .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 + arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 14 + drivers/clk/renesas/Makefile | 3 + drivers/clk/renesas/r9a09g047-cpg.c | 150 ++ drivers/clk/renesas/r9a09g057-cpg.c | 280 ++++ drivers/clk/renesas/rzv2h-cpg.c | 999 ++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 224 +++ drivers/i2c/busses/i2c-riic.c | 125 +- drivers/pinctrl/renesas/Kconfig | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1229 +++++++++++++---- drivers/pinctrl/renesas/pinctrl-rzv2m.c | 3 +- drivers/pinctrl/renesas/pinctrl.c | 3 +- drivers/soc/renesas/Kconfig | 5 + drivers/tty/serial/sh-sci.c | 160 ++- .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 + .../dt-bindings/clock/renesas,r9a09g057-cpg.h | 21 + .../pinctrl/renesas,r9a09g047-pinctrl.h | 41 + .../pinctrl/renesas,r9a09g057-pinctrl.h | 31 + include/linux/serial_sci.h | 1 + include/linux/string.h | 1 + mm/util.c | 17 + 33 files changed, 3747 insertions(+), 414 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.h create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h create mode 100644 include/dt-bindings/clock/renesas,r9a09g057-cpg.h create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h