From patchwork Thu May 16 09:39:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10946199 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BC45912 for ; Thu, 16 May 2019 09:43:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A01428ABC for ; Thu, 16 May 2019 09:43:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F257F28B10; Thu, 16 May 2019 09:43:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5D36D28AFA for ; Thu, 16 May 2019 09:43:42 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 9A32EDC1; Thu, 16 May 2019 09:41:17 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id C67A2DBC for ; Thu, 16 May 2019 09:41:16 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 14F4587D for ; Thu, 16 May 2019 09:41:15 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,476,1549897200"; d="scan'208";a="15924362" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 16 May 2019 18:41:15 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7E08140B4BAB; Thu, 16 May 2019 18:41:14 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Thu, 16 May 2019 10:39:52 +0100 Message-Id: <1557999604-1117-41-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557999604-1117-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557999604-1117-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH v2 40/52] ARM: dts: r8a77470: Add SCIF support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das commit 8cdb8f1ab7efbd88868d3067ec1f211ff289bc01 upstream. Describe SCIF ports in the R8A77470 device tree. Also it fixes the CPG clock index ZS from 6 to 5. Fixes: 6929dfc5918049 ("ARM: dts: r8a77470: Initial SoC device tree") Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [fab: reworked to make it fit 4.4.y-cip definitions, like include files, and properties like clocks, clock-names, and power-domains. Also, removed resets properties as not applicable here. Finally, the fix for the ZS clock index is not applicable to this version] Signed-off-by: Fabrizio Castro --- v1->v2: * No change --- arch/arm/boot/dts/r8a77470.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index d9a89fa..2d542b3 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -177,6 +177,17 @@ reg = <0 0xe6300000 0 0x20000>; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF0>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + scif1: serial@e6e68000 { compatible = "renesas,scif-r8a77470", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; @@ -188,6 +199,51 @@ status = "disabled"; }; + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF2>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF3>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a77470", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF4>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a77470", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A77470_CLK_SCIF5>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;