From patchwork Wed Aug 28 11:03:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 11118593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B96251398 for ; Wed, 28 Aug 2019 11:07:53 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A15B12189D for ; Wed, 28 Aug 2019 11:07:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A15B12189D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=cip-dev-bounces@lists.cip-project.org Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id E59752B27; Wed, 28 Aug 2019 11:05:00 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp2.linuxfoundation.org (smtp2.linux-foundation.org [172.17.192.36]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 317E32966 for ; Wed, 28 Aug 2019 11:04:40 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp2.linuxfoundation.org (Postfix) with ESMTP id 681B61DE27 for ; Wed, 28 Aug 2019 11:04:39 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.64,440,1559487600"; d="scan'208";a="24929629" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Aug 2019 20:04:39 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.36.196]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2E23F4009407; Wed, 28 Aug 2019 20:04:37 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org Date: Wed, 28 Aug 2019 12:03:16 +0100 Message-Id: <1566990211-24785-46-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566990211-24785-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1566990211-24785-1-git-send-email-fabrizio.castro@bp.renesas.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on smtp2.linux-foundation.org Cc: Biju Das Subject: [cip-dev] [PATCH 4.19.y 45/60] arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org From: Biju Das commit 09f49bcf6f5a62467f4fcda59d6bc38f24d97c36 upstream. This patch adds definitions for L2 cache for the Cortex-A53 CPU cores (512 KiB in size, organized as 32 KiB x 16 ways), adds Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57 + 4 x Cortex-A53), and finally enables the performance monitor unit for the Cortex-A53 cores on the R8A774A1 SoC. Based on work done for r8a7796 SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Simon Horman Signed-off-by: Fabrizio Castro --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 66 ++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f379de8..dde1880 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -79,12 +79,59 @@ clocks =<&cpg CPG_CORE 0>; }; + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE 1>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc 6>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE 1>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc 7>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE 1>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc 8>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE 1>; + }; + L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc 12>; cache-unified; cache-level = <2>; }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; }; extal_clk: extal { @@ -108,6 +155,15 @@ clock-frequency = <0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; + }; + pmu_a57 { compatible = "arm,cortex-a57-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -977,7 +1033,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc 32>; @@ -1037,10 +1093,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clocks - can be overridden by the board */