[PATCH/RFC,4.19.y-cip,14/41] pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand

Message ID	1566991328-25476-15-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive)
State	Accepted
Headers	show Return-Path: <SRS0=2obK=WY=lists.cip-project.org=cip-dev-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CA3B92173E From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> To: cip-dev@lists.cip-project.org Date: Wed, 28 Aug 2019 12:21:41 +0100 Message-Id: <1566991328-25476-15-git-send-email-fabrizio.castro@bp.renesas.com> In-Reply-To: <1566991328-25476-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1566991328-25476-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das <biju.das@bp.renesas.com> Subject: [cip-dev] [PATCH/RFC 4.19.y-cip 14/41] pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org
Series	Fast forward sh-pfc \| expand [PATCH/RFC,4.19.y-cip,00/41] Fast forward sh-pfc [PATCH/RFC,4.19.y-cip,01/41] pinctrl: sh-pfc: Print actual field width for variable-width fields [PATCH/RFC,4.19.y-cip,02/41] pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging [PATCH/RFC,4.19.y-cip,03/41] pinctrl: sh-pfc: Add physical pin multiplexing helper macros [PATCH/RFC,4.19.y-cip,04/41] pinctrl: sh-pfc: Validate pins/marks in pin groups at build time [PATCH/RFC,4.19.y-cip,05/41] pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length [PATCH/RFC,4.19.y-cip,06/41] pinctrl: sh-pfc: Validate fixed-size field widths at build time [PATCH/RFC,4.19.y-cip,07/41] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro [PATCH/RFC,4.19.y-cip,08/41] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro [PATCH/RFC,4.19.y-cip,09/41] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro [PATCH/RFC,4.19.y-cip,10/41] pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields [PATCH/RFC,4.19.y-cip,11/41] pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields [PATCH/RFC,4.19.y-cip,12/41] pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation [PATCH/RFC,4.19.y-cip,13/41] pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variant [PATCH/RFC,4.19.y-cip,14/41] pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand [PATCH/RFC,4.19.y-cip,15/41] pinctrl: sh-pfc: Add new non-GPIO helper macros [PATCH/RFC,4.19.y-cip,16/41] pinctrl: sh-pfc: Correct printk level of group reference warning [PATCH/RFC,4.19.y-cip,17/41] pinctrl: sh-pfc: Mark run-time debug code __init [PATCH/RFC,4.19.y-cip,18/41] pinctrl: sh-pfc: Add check for empty pinmux groups/functions [PATCH/RFC,4.19.y-cip,19/41] pinctrl: sh-pfc: Validate pin tables at runtime [PATCH/RFC,4.19.y-cip,20/41] pinctrl: sh-pfc: r8a7796: Fix VIN versioned groups [PATCH/RFC,4.19.y-cip,21/41] pinctrl: sh-pfc: r8a7796: Add I2C{0, 3, 5} pins, groups and functions [PATCH/RFC,4.19.y-cip,22/41] pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions [PATCH/RFC,4.19.y-cip,23/41] pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions [PATCH/RFC,4.19.y-cip,24/41] pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers [PATCH/RFC,4.19.y-cip,25/41] pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions [PATCH/RFC,4.19.y-cip,26/41] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/r… [PATCH/RFC,4.19.y-cip,27/41] pinctrl: sh-pfc: Add missing #include <linux/errno.h> [PATCH/RFC,4.19.y-cip,28/41] pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions [PATCH/RFC,4.19.y-cip,29/41] pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin [PATCH/RFC,4.19.y-cip,30/41] pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A, B, C} to SEL_ADG{A, B, … [PATCH/RFC,4.19.y-cip,31/41] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFR… [PATCH/RFC,4.19.y-cip,32/41] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D [PATCH/RFC,4.19.y-cip,33/41] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and … [PATCH/RFC,4.19.y-cip,34/41] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0, 1, 3, 4}# pin function defin… [PATCH/RFC,4.19.y-cip,35/41] pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF [PATCH/RFC,4.19.y-cip,36/41] pinctrl: sh-pfc: Add PORT_GP_27 helper macro [PATCH/RFC,4.19.y-cip,37/41] pinctrl: sh-pfc: Move PIN_NONE to shared header file [PATCH/RFC,4.19.y-cip,38/41] pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pins [PATCH/RFC,4.19.y-cip,39/41] pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functions [PATCH/RFC,4.19.y-cip,40/41] pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pins [PATCH/RFC,4.19.y-cip,41/41] pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 0b22fe5..bafc81a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -1265,7 +1265,7 @@ static const u16 pinmux_data[] = { #define __O (SH_PFC_PIN_CFG_OUTPUT) #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN) #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 43541b1..c07fdad 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -1528,7 +1528,7 @@ static const u16 pinmux_data[] = { #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) #define __PD (SH_PFC_PIN_CFG_PULL_DOWN) #define __PU (SH_PFC_PIN_CFG_PULL_UP) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN) #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 087c2b3..c75d48f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -13,9 +13,7 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ @@ -1493,17 +1491,17 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 32be7e3..d27a9c7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -14,9 +14,7 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ @@ -1553,17 +1551,17 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index fd9ec59..70b05f2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -19,9 +19,7 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ @@ -1559,16 +1557,16 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index 1ef3960..77661cb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -17,9 +17,7 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ @@ -1561,16 +1559,16 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c index fadfe22..b654e06 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c @@ -16,8 +16,7 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN) #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index b3e1baf..39b86da 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -1160,7 +1160,7 @@ static const u16 pinmux_data[] = { #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) #define __PD (SH_PFC_PIN_CFG_PULL_DOWN) #define __PU (SH_PFC_PIN_CFG_PULL_UP) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN) #define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) #define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 654dc20..d0f56ed 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -570,8 +570,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - return pin->configs & - (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); + return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN; case PIN_CONFIG_BIAS_PULL_UP: return pin->configs & SH_PFC_PIN_CFG_PULL_UP; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 2ee4c79..22df2e2 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -28,6 +28,8 @@ enum { #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) +#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ + SH_PFC_PIN_CFG_PULL_DOWN) #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)

[PATCH/RFC,4.19.y-cip,14/41] pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand

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