From patchwork Mon Sep 2 15:57:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11126945 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 412F1112C for ; Mon, 2 Sep 2019 16:06:00 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29817217D7 for ; Mon, 2 Sep 2019 16:06:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 29817217D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=cip-dev-bounces@lists.cip-project.org Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id A13D8DE1; Mon, 2 Sep 2019 16:04:59 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id AA019E9A for ; Mon, 2 Sep 2019 16:04:58 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 21BCA894 for ; Mon, 2 Sep 2019 16:04:58 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.64,459,1559487600"; d="scan'208";a="25546502" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Sep 2019 01:04:57 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id DBBC140062B8; Tue, 3 Sep 2019 01:04:56 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org Date: Mon, 2 Sep 2019 16:57:54 +0100 Message-Id: <1567439876-1886-21-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567439876-1886-1-git-send-email-biju.das@bp.renesas.com> References: <1567439876-1886-1-git-send-email-biju.das@bp.renesas.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on smtp1.linux-foundation.org Cc: Biju Das Subject: [cip-dev] [PATCH 4.19.y-cip 20/22] arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhz X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org commit 5f5249497bd7ed65d90cac36c3c3dabcda2903dd upstream. Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on dhrystone. Based on work done by Gaku Inami for r8a7796 SoC. The average dhrystone result for 5 iterations is as below: r8a774a1 SoC (CA57x2 + CA53x4) CPU max-freq dhrystone --------------------------------- CA57 1500 MHz 11428571 lps/s CA53 1200 MHz 5000000 lps/s From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated as follows: r8a774a1 SoC CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024 CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) = 560 Since each CPUs have different max frequencies, the final CPU capacities of A53 scaled by the above difference is as below $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 448 448 448 448 Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 50f3f17..0e755b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -137,6 +137,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; }; a57_1: cpu@1 { @@ -148,6 +149,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; }; a53_0: cpu@100 { @@ -159,6 +161,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_1: cpu@101 { @@ -170,6 +173,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_2: cpu@102 { @@ -181,6 +185,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_3: cpu@103 { @@ -192,6 +197,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; L2_CA57: cache-controller-0 {