From patchwork Thu Nov 14 13:24:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11243777 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AFB513B2 for ; Thu, 14 Nov 2019 13:27:20 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63393206DC for ; Thu, 14 Nov 2019 13:27:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63393206DC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=cip-dev-bounces@lists.cip-project.org Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id B473EFE0; Thu, 14 Nov 2019 13:26:34 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp2.linuxfoundation.org (smtp2.linux-foundation.org [172.17.192.36]) by mail.linuxfoundation.org (Postfix) with ESMTPS id EDDDBF7A for ; Thu, 14 Nov 2019 13:26:33 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp2.linuxfoundation.org (Postfix) with ESMTP id CCFD91DCF0 for ; Thu, 14 Nov 2019 13:26:31 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.68,304,1569250800"; d="scan'208";a="31692157" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Nov 2019 22:26:31 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D5CB7422B912; Thu, 14 Nov 2019 22:26:29 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Date: Thu, 14 Nov 2019 13:24:33 +0000 Message-Id: <1573737877-11733-18-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573737877-11733-1-git-send-email-biju.das@bp.renesas.com> References: <1573737877-11733-1-git-send-email-biju.das@bp.renesas.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on smtp2.linux-foundation.org Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y-cip 17/21] ARM: dts: r8a7744: Initial SoC device tree X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org commit d83010f87ab31861eacac1ffe1278f655a376268 upstream. Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman Signed-off-by: Biju Das [ Reworked on clock, reset and power-domains property ] --- arch/arm/boot/dts/r8a7744.dtsi | 778 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 778 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7744.dtsi diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi new file mode 100644 index 0000000..23afef3 --- /dev/null +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -0,0 +1,778 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7744 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a7744"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg_clocks R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&cpg_clocks>; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&cpg_clocks>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + reg = <0 0xe6050000 0 0x50>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + /* placeholder */ + }; + + gpio1: gpio@e6051000 { + reg = <0 0xe6051000 0 0x50>; + #gpio-cells = <2>; + /* placeholder */ + }; + + gpio2: gpio@e6052000 { + reg = <0 0xe6052000 0 0x50>; + #gpio-cells = <2>; + /* placeholder */ + }; + + gpio6: gpio@e6055400 { + reg = <0 0xe6055400 0 0x50>; + #gpio-cells = <2>; + /* placeholder */ + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7744"; + reg = <0 0xe6060000 0 0x250>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7744-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe6530000 0 0x40>; + /* placeholder */ + }; + + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe6528000 0 0x40>; + /* placeholder */ + }; + + hsusb: usb@e6590000 { + reg = <0 0xe6590000 0 0x100>; + /* placeholder */ + }; + + usbphy: usb-phy@e6590100 { + reg = <0 0xe6590100 0 0x100>; + /* placeholder */ + }; + + avb: ethernet@e6800000 { + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + /* placeholder */ + }; + + scifb1: serial@e6c30000 { + reg = <0 0xe6c30000 0 0x100>; + /* placeholder */ + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&mstp7_clks R8A7744_CLK_SCIF0>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + reg = <0 0xe6e68000 0 0x40>; + /* placeholder */ + }; + + hscif1: serial@e62c8000 { + reg = <0 0xe62c8000 0 0x60>; + /* placeholder */ + }; + + can0: can@e6e80000 { + reg = <0 0xe6e80000 0 0x1000>; + /* placeholder */ + }; + + can1: can@e6e88000 { + reg = <0 0xe6e88000 0 0x1000>; + /* placeholder */ + }; + + rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>; + + rcar_sound,dvc { + dvc0: dvc-0 {}; + dvc1: dvc-1 {}; + }; + + rcar_sound,src { + src2: src-2 {}; + src3: src-3 {}; + }; + + rcar_sound,ssi { + ssi0: ssi-0 {}; + ssi1: ssi-1 {}; + }; + /* placeholder */ + }; + + pci0: pci@ee090000 { + reg = <0 0xee090000 0 0xc00>; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + /* placeholder */ + }; + + pci1: pci@ee0d0000 { + reg = <0 0xee0d0000 0 0xc00>; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + /* placeholder */ + }; + + sdhi1: sd@ee140000 { + reg = <0 0xee140000 0 0x100>; + /* placeholder */ + }; + + sdhi2: sd@ee160000 { + reg = <0 0xee160000 0 0x100>; + /* placeholder */ + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&mstp4_clks R8A7744_CLK_INTC_SYS>; + clock-names = "clk"; + power-domains = <&cpg_clocks>; + }; + + du: display@feb00000 { + reg = <0 0xfeb00000 0 0x40000>, + <0 0xfeb90000 0 0x1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + /* placeholder */ + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7744-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk &usb_extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", + "pll3", "lb", "qspi", + "sdh", "sd0", "z", "rcan"; + #power-domain-cells = <0>; + }; + + /* Variable factor clocks */ + sd2_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a7744-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + sd3_clk: sd3_clk@e615026c { + compatible = "renesas,r8a7744-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe615026c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd3"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a7744-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <5>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7744_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "msiof0"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, + <&zg_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, + <&rclk_clk>, <&cp_clk>, <&zs_clk>, + <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_VCP0 R8A7744_CLK_VPC0 + R8A7744_CLK_TMU1 R8A7744_CLK_3DG + R8A7744_CLK_2DDMAC R8A7744_CLK_FDP1_1 + R8A7744_CLK_FDP1_0 R8A7744_CLK_TMU3 + R8A7744_CLK_TMU2 R8A7744_CLK_CMT0 + R8A7744_CLK_TMU0 R8A7744_CLK_VSP1_DU1 + R8A7744_CLK_VSP1_DU0 R8A7744_CLK_VSP1_S + >; + clock-output-names = + "vcp0", "vpc0", "tmu1", "3dg", + "2ddmac", "fdp1-1", "fdp1-0", "tmu3", + "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&zs_clk>, + <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_SCIFA2 R8A7744_CLK_SCIFA1 + R8A7744_CLK_SCIFA0 R8A7744_CLK_MSIOF2 + R8A7744_CLK_SCIFB0 R8A7744_CLK_SCIFB1 + R8A7744_CLK_MSIOF1 R8A7744_CLK_SCIFB2 + R8A7744_CLK_SYS_DMAC1 + R8A7744_CLK_SYS_DMAC0 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "msiof2", + "scifb0", "scifb1", "msiof1", "scifb2", + "sys-dmac1", "sys-dmac0"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, + <&cpg_clocks R8A7744_CLK_SD0>, + <&mmc0_clk>, <&hp_clk>, <&mp_clk>, + <&hp_clk>, <&mp_clk>, <&rclk_clk>, + <&hp_clk>, <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_TPU0 R8A7744_CLK_SDHI2 + R8A7744_CLK_SDHI1 R8A7744_CLK_SDHI0 + R8A7744_CLK_MMCIF0 R8A7744_CLK_IIC0 + R8A7744_CLK_PCIEC R8A7744_CLK_IIC1 + R8A7744_CLK_SSUSB R8A7744_CLK_CMT1 + R8A7744_CLK_USBDMAC0 + R8A7744_CLK_USBDMAC1 + >; + clock-output-names = + "tpu0", "sdhi3", "sdhi2", "sdhi0", + "mmcif0", "i2c7", "pciec", "i2c8", + "ssusb", "cmt1", "usbdmac0", + "usbdmac1"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&rclk_clk>, <&cp_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_RWDT R8A7744_CLK_IRQC + R8A7744_CLK_INTC_SYS + >; + clock-output-names = "rwdt", "irqc", "intc-sys"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&hp_clk>, <&hp_clk>, + <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_AUDIO_DMAC0 + R8A7744_CLK_AUDIO_DMAC1 + R8A7744_CLK_THERMAL R8A7744_CLK_PWM + >; + clock-output-names = "audmac0", "audmac1", + "thermal", "pwm"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, + <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&zx_clk>, + <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_USB_EHCI R8A7744_CLK_HSUSB + R8A7744_CLK_HSCIF2 R8A7744_CLK_SCIF5 + R8A7744_CLK_SCIF4 R8A7744_CLK_HSCIF1 + R8A7744_CLK_HSCIF0 R8A7744_CLK_SCIF3 + R8A7744_CLK_SCIF2 R8A7744_CLK_SCIF1 + R8A7744_CLK_SCIF0 R8A7744_CLK_DU1 + R8A7744_CLK_DU0 R8A7744_CLK_LVDS0 + >; + clock-output-names = + "ehci", "hsusb", "hscif2", "scif5", + "scif4", "hscif1", "hscif0", "scif3", + "scif2", "scif1", "scif0", "du1", + "du0", "lvds0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, + <&zg_clk>, <&hp_clk>, <&p_clk>, + <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_IPMMU_SGX + R8A7744_CLK_VIN2 R8A7744_CLK_VIN1 + R8A7744_CLK_VIN0 R8A7744_CLK_ETHERAVB + R8A7744_CLK_ETHER R8A7744_CLK_SATA1 + R8A7744_CLK_SATA0 + >; + clock-output-names = + "ipmmu_sgx", "vin2", "vin1", "vin0", + "etheravb", "ether", "sata1", "sata0"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&p_clk>, + <&p_clk>, + <&cpg_clocks R8A7744_CLK_QSPI>, + <&hp_clk>, <&cp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_GPIO7 R8A7744_CLK_GPIO6 + R8A7744_CLK_GPIO5 R8A7744_CLK_GPIO4 + R8A7744_CLK_GPIO3 R8A7744_CLK_GPIO2 + R8A7744_CLK_GPIO1 R8A7744_CLK_GPIO0 + R8A7744_CLK_RCAN1 R8A7744_CLK_RCAN0 + R8A7744_CLK_QSPI_MOD R8A7744_CLK_I2C5 + R8A7744_CLK_IICDVFS R8A7744_CLK_I2C4 + R8A7744_CLK_I2C3 R8A7744_CLK_I2C2 + R8A7744_CLK_I2C1 R8A7744_CLK_I2C0 + >; + clock-output-names = + "gpio7", "gpio6", "gpio5", "gpio4", + "gpio3", "gpio2", "gpio1", "gpio0", + "rcan1", "rcan0", "qspi_mod", "i2c5", + "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", + "i2c0"; + }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, + <&p_clk>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>, + <&mstp10_clks R8A7744_CLK_SCU_ALL>; + + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_SSI_ALL + R8A7744_CLK_SSI9 R8A7744_CLK_SSI8 + R8A7744_CLK_SSI7 R8A7744_CLK_SSI6 + R8A7744_CLK_SSI5 R8A7744_CLK_SSI4 + R8A7744_CLK_SSI3 R8A7744_CLK_SSI2 + R8A7744_CLK_SSI1 R8A7744_CLK_SSI0 + R8A7744_CLK_SCU_ALL + R8A7744_CLK_SCU_DVC1 + R8A7744_CLK_SCU_DVC0 + R8A7744_CLK_SCU_CTU1_MIX1 + R8A7744_CLK_SCU_CTU0_MIX0 + R8A7744_CLK_SCU_SRC9 + R8A7744_CLK_SCU_SRC8 + R8A7744_CLK_SCU_SRC7 + R8A7744_CLK_SCU_SRC6 + R8A7744_CLK_SCU_SRC5 + R8A7744_CLK_SCU_SRC4 + R8A7744_CLK_SCU_SRC3 + R8A7744_CLK_SCU_SRC2 + R8A7744_CLK_SCU_SRC1 + R8A7744_CLK_SCU_SRC0 + >; + clock-output-names = + "ssi-all", + "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", + "scu-all", + "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", + "scu-src9", "scu-src8", "scu-src7", + "scu-src6", "scu-src5", "scu-src4", + "scu-src3", "scu-src2", "scu-src1", + "scu-src0"; + }; + mstp11_clks: mstp11_clks@e615099c { + compatible = "renesas,r8a7744-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7744_CLK_SCIFA3 R8A7744_CLK_SCIFA4 + R8A7744_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", + "scifa5"; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +};