From patchwork Tue Nov 19 14:53:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11252287 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B6A3138C for ; Tue, 19 Nov 2019 14:55:29 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83399222A0 for ; Tue, 19 Nov 2019 14:55:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 83399222A0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=cip-dev-bounces@lists.cip-project.org Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 7841286999; Tue, 19 Nov 2019 14:55:29 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yudmx2b6LOrn; Tue, 19 Nov 2019 14:55:27 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by fraxinus.osuosl.org (Postfix) with ESMTP id 945F886992; Tue, 19 Nov 2019 14:55:27 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 7C715C07AC; Tue, 19 Nov 2019 14:55:27 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@lists.linuxfoundation.org Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by lists.linuxfoundation.org (Postfix) with ESMTP id 0BE67C07AC for ; Tue, 19 Nov 2019 14:55:26 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id EEFFD87668 for ; Tue, 19 Nov 2019 14:55:25 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7cIfnqibxeTE for ; Tue, 19 Nov 2019 14:55:25 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by whitealder.osuosl.org (Postfix) with ESMTP id E16FC87667 for ; Tue, 19 Nov 2019 14:55:24 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.68,324,1569250800"; d="scan'208";a="32096071" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 19 Nov 2019 23:55:24 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C784B40083DC; Tue, 19 Nov 2019 23:55:22 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Date: Tue, 19 Nov 2019 14:53:33 +0000 Message-Id: <1574175222-52858-9-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574175222-52858-1-git-send-email-biju.das@bp.renesas.com> References: <1574175222-52858-1-git-send-email-biju.das@bp.renesas.com> Cc: Biju Das Subject: [cip-dev] [PATCH 4.4.y-cip 08/17] ARM: dts: r8a7744: Add SMP support X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: cip-dev-bounces@lists.cip-project.org Sender: "cip-dev" commit f1546da8a5c8862d1e66835affcfaf9a0c123abc upstream. Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Also add cpu1 phandle node to the PMU interrupt-affinity property. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman [biju: removed resets property. Updated power-domains and clocks properties] Signed-off-by: Biju Das --- arch/arm/boot/dts/r8a7744.dtsi | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index b0c4be2..e712b13 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -48,6 +48,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -68,6 +69,25 @@ < 375000 1000000>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg_clocks R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&cpg_clocks>; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + L2_CA15: cache-controller-0 { compatible = "cache"; cache-unified; @@ -95,7 +115,7 @@ compatible = "arm,cortex-a15-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; + interrupt-affinity = <&cpu0>, <&cpu1>; }; /* External SCIF clock */ @@ -231,6 +251,12 @@ reg = <0 0xe6060000 0 0x250>; }; + apmu@e6152000 { + compatible = "renesas,r8a7744-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + rst: reset-controller@e6160000 { compatible = "renesas,r8a7744-rst"; reg = <0 0xe6160000 0 0x100>; @@ -454,7 +480,7 @@ interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; + interrupts = ; clocks = <&mstp4_clks R8A7744_CLK_INTC_SYS>; clock-names = "clk"; power-domains = <&cpg_clocks>; @@ -918,10 +944,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */