From patchwork Mon Jun 8 09:14:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11593227 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 693AC1667 for ; Mon, 8 Jun 2020 12:01:39 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 434D72078C for ; Mon, 8 Jun 2020 12:01:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="IjnhErbE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 434D72078C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+4767+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id qNAwYY4521763x7fX8PsMM5A; Mon, 08 Jun 2020 05:01:39 -0700 X-Received: from wens.tw (wens.tw [140.112.30.76]) by mx.groups.io with SMTP id smtpd.web12.26176.1591607689005962385 for ; Mon, 08 Jun 2020 02:14:49 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id BA9815FD80; Mon, 8 Jun 2020 17:14:43 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com Subject: [cip-dev] [PATCH 4.4.y-cip v2 04/15] PM / OPP: Remove 'operating-points-names' binding Date: Mon, 8 Jun 2020 17:14:21 +0800 Message-Id: <20200608091432.15366-5-wens@csie.org> In-Reply-To: <20200608091432.15366-1-wens@csie.org> References: <20200608091432.15366-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 9G8fuMGlbaIJFCPTtly7a6dJx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1591617699; bh=hlaAbra8gLLEVfSedvWg9IkW7UiAEUM6s87bxF4Zxes=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=IjnhErbE61nL6QUl8cOKjW3TSpGsWyFJO0cD3F/SIkJX06+CZrgb3fo/4ttzz7A74YQ 62M1BrYFhKAfQooSH7I7na5PlPQ2sQZ/7p5oM5W6zS5G/qmZ5vQmWxdYOC5B/V36x8lTC mecG9bjmVbqSJGgnp3fkRTE1Ze90mxXffyo= From: Viresh Kumar commit af87a39a5f7cf6ef252b1aec3e2e6508a40e51f1 upstream. These aren't used until now by any DT files and wouldn't be used now as we have a better scheme in place now, i.e. opp-property- properties. Remove the (useless) binding without breaking ABI. Reviewed-by: Stephen Boyd Acked-by: Rob Herring Signed-off-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- Documentation/devicetree/bindings/opp/opp.txt | 62 +------------------ 1 file changed, 2 insertions(+), 60 deletions(-) diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index a3e7f0d5e1fb4..24eac9a977494 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -45,21 +45,10 @@ Devices supporting OPPs must set their "operating-points-v2" property with phandle to a OPP table in their DT node. The OPP core will use this phandle to find the operating points for the device. -Devices may want to choose OPP tables at runtime and so can provide a list of -phandles here. But only *one* of them should be chosen at runtime. This must be -accompanied by a corresponding "operating-points-names" property, to uniquely -identify the OPP tables. - If required, this can be extended for SoC vendor specfic bindings. Such bindings should be documented as Documentation/devicetree/bindings/power/-opp.txt and should have a compatible description like: "operating-points-v2-". -Optional properties: -- operating-points-names: Names of OPP tables (required if multiple OPP - tables are present), to uniquely identify them. The same list must be present - for all the CPUs which are sharing clock/voltage rails and hence the OPP - tables. - * OPP Table Node This describes the OPPs belonging to a device. This node can have following @@ -448,54 +437,7 @@ Example 4: Handling multiple regulators }; }; -Example 5: Multiple OPP tables - -/ { - cpus { - cpu@0 { - compatible = "arm,cortex-a7"; - ... - - cpu-supply = <&cpu_supply> - operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>; - operating-points-names = "slow", "fast"; - }; - }; - - cpu0_opp_table_slow: opp_table_slow { - compatible = "operating-points-v2"; - status = "okay"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <600000000>; - ... - }; - - opp01 { - opp-hz = /bits/ 64 <800000000>; - ... - }; - }; - - cpu0_opp_table_fast: opp_table_fast { - compatible = "operating-points-v2"; - status = "okay"; - opp-shared; - - opp10 { - opp-hz = /bits/ 64 <1000000000>; - ... - }; - - opp11 { - opp-hz = /bits/ 64 <1100000000>; - ... - }; - }; -}; - -Example 6: opp-supported-hw +Example 5: opp-supported-hw (example: three level hierarchy of versions: cuts, substrate and process) / { @@ -540,7 +482,7 @@ Example 6: opp-supported-hw }; }; -Example 7: opp-microvolt-, opp-microamp-: +Example 6: opp-microvolt-, opp-microamp-: (example: device with two possible microvolt ranges: slow and fast) / {