From patchwork Wed Jul 8 15:45:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11651841 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29E5A13B4 for ; Wed, 8 Jul 2020 15:46:37 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 040BE20786 for ; Wed, 8 Jul 2020 15:46:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="nByeNDxG" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 040BE20786 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+4896+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id sVFLYY4521763xOXsDIUbyCK; Wed, 08 Jul 2020 08:46:34 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web11.13703.1594223182933119721 for ; Wed, 08 Jul 2020 08:46:23 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id 5C6B35FE3B; Wed, 8 Jul 2020 23:46:17 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com Subject: [cip-dev] [PATCH 4.4.y-cip 10/23] cpufreq: dt: OPP layers handles clock-latency for V1 bindings as well Date: Wed, 8 Jul 2020 23:45:41 +0800 Message-Id: <20200708154554.26450-11-wens@csie.org> In-Reply-To: <20200708154554.26450-1-wens@csie.org> References: <20200708154554.26450-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: lnDIyrJs2lTwzDdqEU0a1RgEx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1594223194; bh=IyNf6cu90hXUs4Zji2oM9hMb42kQDRKCU+DQT9xf5cg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=nByeNDxG+2n7ajvdDf/vMA/SxqzqiZXCQeFyTGGF46wS+Dgi6dpEr9mo/D7FZpWLZwZ qZIkAEwz/b8nKq3ArtyigkcvvtkEgSuEQcqmaPm8ZF5UX7/Wpnq5FGlqk6pb7JiIjbgrZ 8uOx3f0FbuLvBnvhX5xEEHsYVvRqg7HGTYw= From: Viresh Kumar commit 391d9aef8145204e0a5d67be3bd1fc45c5396dae upstream. "clock-latency" is handled by OPP layer for all bindings and so there is no need to make special calls for V1 bindings. Use dev_pm_opp_get_max_clock_latency() for both the cases. Signed-off-by: Viresh Kumar Reviewed-by: Stephen Boyd Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- drivers/cpufreq/cpufreq-dt.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c index 0047d20803db7..4c9f8a828f6f1 100644 --- a/drivers/cpufreq/cpufreq-dt.c +++ b/drivers/cpufreq/cpufreq-dt.c @@ -265,10 +265,6 @@ static int cpufreq_init(struct cpufreq_policy *policy) if (ret) dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n", __func__, ret); - - of_property_read_u32(np, "clock-latency", &transition_latency); - } else { - transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev); } priv = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -279,6 +275,7 @@ static int cpufreq_init(struct cpufreq_policy *policy) of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance); + transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev); if (!transition_latency) transition_latency = CPUFREQ_ETERNAL;