From patchwork Fri Aug 21 09:43:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729121 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C3D561575 for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E45E207BB for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="Ie8ez7Us" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9E45E207BB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5209+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id GPx1YY4521763x1Q3hNi4Ob5; Fri, 21 Aug 2020 03:58:46 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.130436.1598003042737837811 for ; Fri, 21 Aug 2020 02:44:03 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170357" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:02 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id ABBB94232061; Fri, 21 Aug 2020 18:44:00 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 25/36] pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functions Date: Fri, 21 Aug 2020 10:43:01 +0100 Message-Id: <20200821094312.3249-26-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: zJstRY3HNHqo4mDcei9N5APVx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007526; bh=bIza8gYcZVXYSeuAu64ayD5BZVhhKTRtdmOh5uaOJgg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Ie8ez7Us2jmKuCtPgFy+yam5sq8ioSeWjscp2KvDNdHe1/f/2Mzc4b3AleZbPsWuCwo R0ZRyijx+U4W3hZw5ijd4A7PJrQHByXGlp1a1Zr9KLCu6J+1Tf2hILSby2VmYj7vIKiZ9 9oKbq8nG03HZ4FZptrDoh+KvOtk1u4blif8= From: Geert Uytterhoeven commit 9141d4558fcc635c4ec3b5ddd99f24d8df7fe6e0 upstream. Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revisions ES2.x and later of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 944dfd943541..054fec90eded 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -3901,6 +3901,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4451,6 +4481,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), @@ -4946,6 +4980,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -5048,6 +5089,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2),