| Message ID | 20201201083938.32688-12-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Nobuhiro Iwamatsu |
| Headers | show |
| Series | Renesas RZ/G1x add SoC detection support | expand |
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 1057bff76cc8..3bf1a458593b 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -715,6 +715,11 @@ power-domains = <&cpg_clocks>; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + cmt0: timer@ffca0000 { compatible = "renesas,cmt-48-r8a77470", "renesas,cmt-48-gen2";
Add a device node for the Product Register, which provides SoC product and revision information. PRR node is added as part of upstream commit 6929dfc591804 ("ARM: dts: r8a77470: Initial SoC device tree") as this commit includes initial SoC DTSI PRR node cannot be individually backported hence this new commit. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm/boot/dts/r8a77470.dtsi | 5 +++++ 1 file changed, 5 insertions(+)