From patchwork Tue Jan 5 15:10:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 11999207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,SPF_HELO_NONE,SPF_PASS, T_TVD_MIME_NO_HEADERS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 385FDC433E0 for ; Tue, 5 Jan 2021 15:11:11 +0000 (UTC) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF97A22B4B for ; Tue, 5 Jan 2021 15:11:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BF97A22B4B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+6029+4520388+8129055@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id cI2mYY4521723xcf6AjX8QII; Tue, 05 Jan 2021 07:11:10 -0800 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web09.6601.1609859461949547050 for ; Tue, 05 Jan 2021 07:11:09 -0800 X-IronPort-AV: E=Sophos;i="5.78,477,1599490800"; d="scan'208";a="67872247" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Jan 2021 00:11:09 +0900 X-Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 49CA5400A0F2; Wed, 6 Jan 2021 00:11:08 +0900 (JST) From: "Lad Prabhakar" To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [cip-dev] [PATCH 4.19.y-cip 7/8] pinctrl: renesas: r8a7796: Add QSPI[01] pins, groups and functions Date: Tue, 5 Jan 2021 15:10:56 +0000 Message-Id: <20210105151057.12752-8-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20210105151057.12752-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20210105151057.12752-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: OXxygcq9NBQKZRDYFwWAYjx8x4520388AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1609859470; bh=RUPpNk5uyK2STtvv/8lQLzLuQ3Rd4L0jq0J1rruAd3U=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ropF0OFV/9VTG7xtAcnVG+M9PmR0PyryUG/rkaSbiHQVparxQNa45PZYr2oYUW61y7H 5dKZRNV/lgY1JzgnzMt5Q9NRGp2c+es8oR0/MRa3MDwvVhKUOT24c25wDVQix0A431E1m j2xURN50/kPAjk2BAQ423sxRBHZna65Zt1g= commit 4356497e9eda8ec7dcd095b1ecd947ffe12917aa upstream. Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201119130926.25692-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [PL: Manually applied the changes] Signed-off-by: Lad Prabhakar --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 75 +++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index b9c857ce3328..91afbcf4d513 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -3260,6 +3260,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -4137,7 +4188,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[316]; + struct sh_pfc_pin_group common[322]; #if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_pin_group automotive[30]; #endif @@ -4342,6 +4393,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4832,6 +4889,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -5007,7 +5076,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[50]; + struct sh_pfc_function common[52]; #if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_function automotive[4]; #endif @@ -5044,6 +5113,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2),