diff mbox series

[5.10.y-cip,25/27] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board

Message ID 20220131121903.8620-26-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add RPCIF, SCI{F1} support to Renesas RZ/G2L SoC | expand

Commit Message

Lad Prabhakar Jan. 31, 2022, 12:19 p.m. UTC
commit 5a8aa63c9bca800e6049d90422abe5404227a703 upstream.

SCIF2 interface is available on PMOD1 connector (CN7) on carrier board,
This patch adds pinmux and scif2 node to carrier board dtsi file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103195600.23964-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied the changes.]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 28 ++++++++++++++++++++
 1 file changed, 28 insertions(+)

Comments

Pavel Machek Feb. 1, 2022, 11:11 a.m. UTC | #1
Hi!

> commit 5a8aa63c9bca800e6049d90422abe5404227a703 upstream.
> 
> SCIF2 interface is available on PMOD1 connector (CN7) on carrier board,
> This patch adds pinmux and scif2 node to carrier board dtsi file.


> +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> @@ -8,9 +8,13 @@
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>  
> +/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
> +#define PMOD1_SER0	1
> +

AFAICT this needs to be set to 0, not commented out.


> @@ -156,6 +167,23 @@
>  	status = "okay";
>  };
>  
> +/*
> + * To enable SCIF2 (SER0) on PMOD1 (CN7)
> + * SW1 should be at position 2->3 so that SER0_CTS# line is activated
> + * SW2 should be at position 2->3 so that SER0_TX line is activated
> + * SW3 should be at position 2->3 so that SER0_RX line is activated
> + * SW4 should be at position 2->3 so that SER0_RTS# line is activated
> + */
> +#if PMOD1_SER0
> +&scif2 {
> +	pinctrl-0 = <&scif2_pins>;
> +	pinctrl-names = "default";
> +
> +	uart-has-rtscts;
> +	status = "okay";
> +};
> +#endif
> +
>  &usb2_phy0 {
>  	pinctrl-0 = <&usb0_pins>;
>  	pinctrl-names = "default";

Best regards,
								Pavel
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index a33594575fc4..70aca5d0306d 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -8,9 +8,13 @@ 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
+/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0	1
+
 / {
 	aliases {
 		serial0 = &scif0;
+		serial1 = &scif2;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		i2c3 = &i2c3;
@@ -138,6 +142,13 @@ 
 			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
 	};
 
+	scif2_pins: scif2 {
+		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
+			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
+			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
+			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
+	};
+
 	usb0_pins: usb0 {
 		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
 			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
@@ -156,6 +167,23 @@ 
 	status = "okay";
 };
 
+/*
+ * To enable SCIF2 (SER0) on PMOD1 (CN7)
+ * SW1 should be at position 2->3 so that SER0_CTS# line is activated
+ * SW2 should be at position 2->3 so that SER0_TX line is activated
+ * SW3 should be at position 2->3 so that SER0_RX line is activated
+ * SW4 should be at position 2->3 so that SER0_RTS# line is activated
+ */
+#if PMOD1_SER0
+&scif2 {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	status = "okay";
+};
+#endif
+
 &usb2_phy0 {
 	pinctrl-0 = <&usb0_pins>;
 	pinctrl-names = "default";