[5.10.y-cip,20/29] arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog

From: Biju Das <biju.das.jz@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 20/29] arm64: dts: renesas: rzg2l-smarc-som: Enable
 watchdog
Date: Mon,  4 Apr 2022 13:35:44 +0100
Message-Id: <20220404123553.25851-21-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20220404123553.25851-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20220404123553.25851-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Message ID	20220404123553.25851-21-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Nobuhiro Iwamatsu
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH 5.10.y-cip 20/29] arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog Date: Mon, 4 Apr 2022 13:35:44 +0100 Message-Id: <20220404123553.25851-21-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20220404123553.25851-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220404123553.25851-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Series	Add RSPI/OSTM/WDT/TSU/OPP support to Renesas RZ/G2L SoC \| expand [5.10.y-cip,00/29] Add RSPI/OSTM/WDT/TSU/OPP support to Renesas RZ/G2L SoC [5.10.y-cip,01/29] clk: renesas: r9a07g044: Add RSPI clock and reset entries [5.10.y-cip,02/29] spi: dt-bindings: renesas,rspi: Document RZ/G2L SoC [5.10.y-cip,03/29] spi: spi-rspi: Add support to deassert/assert reset line [5.10.y-cip,04/29] spi: spi-rspi: Drop redeclaring ret variable in qspi_transfer_in() [5.10.y-cip,05/29] arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes [5.10.y-cip,06/29] arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board [5.10.y-cip,07/29] clk: renesas: r9a07g044: Add WDT clock and reset entries [5.10.y-cip,08/29] clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros [5.10.y-cip,09/29] dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L [5.10.y-cip,10/29] units: Add SI metric prefix definitions [5.10.y-cip,11/29] watchdog: Add Watchdog Timer driver for RZ/G2L [5.10.y-cip,12/29] clk: renesas: r9a07g044: Add OSTM clock and reset entries [5.10.y-cip,13/29] dt-bindings: timer: renesas: ostm: Document Renesas RZ/G2L OSTM [5.10.y-cip,14/29] reset: Add of_reset_control_get_optional_exclusive() [5.10.y-cip,15/29] clocksource/drivers/renesas-ostm: Add RZ/G2L OSTM support [5.10.y-cip,16/29] clocksource/drivers/renesas,ostm: Make RENESAS_OSTM symbol visible [5.10.y-cip,17/29] arm64: dts: renesas: r9a07g044: Add OSTM nodes [5.10.y-cip,18/29] arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM [5.10.y-cip,19/29] arm64: dts: renesas: r9a07g044: Add WDT nodes [5.10.y-cip,20/29] arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog [5.10.y-cip,21/29] clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV [5.10.y-cip,22/29] clk: renesas: r9a07g044: Add TSU clock and reset entry [5.10.y-cip,23/29] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro [5.10.y-cip,24/29] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro [5.10.y-cip,25/29] dt-bindings: thermal: Document Renesas RZ/G2L TSU [5.10.y-cip,26/29] thermal/drivers: Add TSU driver for RZ/G2L [5.10.y-cip,27/29] arm64: dts: renesas: r9a07g044: Add OPP table [5.10.y-cip,28/29] arm64: dts: renesas: r9a07g044: Add TSU node [5.10.y-cip,29/29] arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA

[5.10.y-cip,20/29] arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog

Commit Message

Patch