diff mbox series

[isar-cip-core,1/2] .gitlabci: add qemu-arm64 secureboot and swupdate

Message ID 20220610072524.910925-2-Quirin.Gylstorff@siemens.com (mailing list archive)
State Handled Elsewhere
Headers show
Series Update CI builds | expand

Commit Message

Gylstorff Quirin June 10, 2022, 7:25 a.m. UTC
From: Quirin Gylstorff <quirin.gylstorff@siemens.com>

Signed-off-by: Quirin Gylstorff <quirin.gylstorff@siemens.com>
---
 .gitlab-ci.yml | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Jan Kiszka June 13, 2022, 9:30 a.m. UTC | #1
On 10.06.22 09:25, Quirin Gylstorff wrote:
> From: Quirin Gylstorff <quirin.gylstorff@siemens.com>
> 
> Signed-off-by: Quirin Gylstorff <quirin.gylstorff@siemens.com>
> ---
>  .gitlab-ci.yml | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
> index 8545a66..23ab1cb 100644
> --- a/.gitlab-ci.yml
> +++ b/.gitlab-ci.yml
> @@ -218,6 +218,29 @@ build:qemu-amd64-swupdate:
>      targz: disable
>      deploy: disable
>  
> +# secure boot images arm64
> +build:qemu-arm64-secure-boot:
> +  extends:
> +    - .build_base
> +  variables:
> +    target: qemu-arm64
> +    extension: ebg-secure-boot-snakeoil
> +    use_rt: disable
> +    wic_targz: disable
> +    targz: disable
> +    deploy: disable
> +
> +build:qemu-arm64-swupdate:
> +  extends:
> +    - .build_base
> +  variables:
> +    target: qemu-arm64
> +    extension: ebg-swu
> +    use_rt: disable
> +    wic_targz: disable
> +    targz: disable
> +    deploy: disable

I think we can skip the second test. The non-secure build variant is
already sufficiently covered by the x86 build, and the non-secure u-boot
build for arm64 is not too special.

Jan

> +
>  # bullseye images
>  build:simatic-ipc227e-bullseye:
>    extends:
Gylstorff Quirin June 13, 2022, 10 a.m. UTC | #2
On 6/13/22 11:30, Jan Kiszka wrote:
> On 10.06.22 09:25, Quirin Gylstorff wrote:
>> From: Quirin Gylstorff <quirin.gylstorff@siemens.com>
>>
>> Signed-off-by: Quirin Gylstorff <quirin.gylstorff@siemens.com>
>> ---
>>   .gitlab-ci.yml | 23 +++++++++++++++++++++++
>>   1 file changed, 23 insertions(+)
>>
>> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
>> index 8545a66..23ab1cb 100644
>> --- a/.gitlab-ci.yml
>> +++ b/.gitlab-ci.yml
>> @@ -218,6 +218,29 @@ build:qemu-amd64-swupdate:
>>       targz: disable
>>       deploy: disable
>>   
>> +# secure boot images arm64
>> +build:qemu-arm64-secure-boot:
>> +  extends:
>> +    - .build_base
>> +  variables:
>> +    target: qemu-arm64
>> +    extension: ebg-secure-boot-snakeoil
>> +    use_rt: disable
>> +    wic_targz: disable
>> +    targz: disable
>> +    deploy: disable
>> +
>> +build:qemu-arm64-swupdate:
>> +  extends:
>> +    - .build_base
>> +  variables:
>> +    target: qemu-arm64
>> +    extension: ebg-swu
>> +    use_rt: disable
>> +    wic_targz: disable
>> +    targz: disable
>> +    deploy: disable
> 
> I think we can skip the second test. The non-secure build variant is
> already sufficiently covered by the x86 build, and the non-secure u-boot
> build for arm64 is not too special.
> 
> Jan

Ok, will send a v2.
> 
>> +
>>   # bullseye images
>>   build:simatic-ipc227e-bullseye:
>>     extends:
> 

Quirin
diff mbox series

Patch

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 8545a66..23ab1cb 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -218,6 +218,29 @@  build:qemu-amd64-swupdate:
     targz: disable
     deploy: disable
 
+# secure boot images arm64
+build:qemu-arm64-secure-boot:
+  extends:
+    - .build_base
+  variables:
+    target: qemu-arm64
+    extension: ebg-secure-boot-snakeoil
+    use_rt: disable
+    wic_targz: disable
+    targz: disable
+    deploy: disable
+
+build:qemu-arm64-swupdate:
+  extends:
+    - .build_base
+  variables:
+    target: qemu-arm64
+    extension: ebg-swu
+    use_rt: disable
+    wic_targz: disable
+    targz: disable
+    deploy: disable
+
 # bullseye images
 build:simatic-ipc227e-bullseye:
   extends: