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[5.10.y-cip,18/24] iio: adc: rzg2l_adc: Fix typo

Message ID	20220715072244.2298757-19-biju.das.jz@bp.renesas.com (mailing list archive)
State	Accepted
Headers	show Return-Path: <biju.das.jz@bp.renesas.com> ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) From: Biju Das <biju.das.jz@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Chris Paterson <chris.paterson2@renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH 5.10.y-cip 18/24] iio: adc: rzg2l_adc: Fix typo Date: Fri, 15 Jul 2022 08:22:38 +0100 Message-Id: <20220715072244.2298757-19-biju.das.jz@bp.renesas.com> In-Reply-To: <20220715072244.2298757-1-biju.das.jz@bp.renesas.com> References: <20220715072244.2298757-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	RZ/G2L Fixes from mainline \| expand [5.10.y-cip,00/24] RZ/G2L Fixes from mainline [5.10.y-cip,01/24] soc: renesas: Consolidate product register handling [5.10.y-cip,02/24] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC [5.10.y-cip,03/24] soc: renesas: Identify RZ/V2L SoC [5.10.y-cip,04/24] soc: renesas: Add support for reading product revision for RZ/G2L family [5.10.y-cip,05/24] soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs [5.10.y-cip,06/24] soc: renesas: Kconfig: Introduce ARCH_RZG2L config option [5.10.y-cip,07/24] ASoC: sh: Make SND_SOC_RZ depend on ARCH_RZG2L [5.10.y-cip,08/24] iio: adc: Kconfig: Make RZG2L_ADC depend on ARCH_RZG2L [5.10.y-cip,09/24] dt-bindings: dma: rz-dmac: Document RZ/V2L SoC [5.10.y-cip,10/24] dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC config option [5.10.y-cip,11/24] dmaengine: sh: Kconfig: Make RZ_DMAC depend on ARCH_RZG2L [5.10.y-cip,12/24] reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L [5.10.y-cip,13/24] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add description for power-source pr… [5.10.y-cip,14/24] ASoC: sh: rz-ssi: Drop SSIFSR_TDC and SSIFSR_RDC macros [5.10.y-cip,15/24] ASoC: sh: rz-ssi: Propagate error codes returned from platform_get_irq_byname() [5.10.y-cip,16/24] ASoC: sh: rz-ssi: Release the DMA channels in rz_ssi_probe() error path [5.10.y-cip,17/24] iio: adc: rzg2l_adc: Remove unnecessary print function dev_err() [5.10.y-cip,18/24] iio: adc: rzg2l_adc: Fix typo [5.10.y-cip,19/24] iio: adc: rzg2l_adc: add missing fwnode_handle_put() in rzg2l_adc_parse_properti… [5.10.y-cip,20/24] reset: renesas: Fix Runtime PM usage [5.10.y-cip,21/24] reset: renesas: Check return value of reset_control_deassert() [5.10.y-cip,22/24] i2c: riic: Simplify reset handling [5.10.y-cip,23/24] arm64: dts: renesas: Fix pin controller node names [5.10.y-cip,24/24] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions

Commit Message

Biju Das July 15, 2022, 7:22 a.m. UTC

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 2553340bd208cc2e54a9e6a27d948a2b51dbf3a1 upstream.

Fix typo RZG2L_ADSMP_DEFUALT_SAMPLING -> RZG2L_ADSMP_DEFAULT_SAMPLING.

Reported-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Link: https://lore.kernel.org/r/20220107172529.12361-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/iio/adc/rzg2l_adc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 4955a91128c8..38fccb7bcd65 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -55,7 +55,7 @@ 
 #define RZG2L_ADCR(n)			(0x30 + ((n) * 0x4))
 #define RZG2L_ADCR_AD_MASK		GENMASK(11, 0)
 
-#define RZG2L_ADSMP_DEFUALT_SAMPLING	0x578
+#define RZG2L_ADSMP_DEFAULT_SAMPLING	0x578
 
 #define RZG2L_ADC_MAX_CHANNELS		8
 #define RZG2L_ADC_CHN_MASK		0x7
@@ -384,7 +384,7 @@  static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
 	reg &= ~RZG2L_ADM3_ADIL_MASK;
 	reg &= ~RZG2L_ADM3_ADCMP_MASK;
 	reg &= ~RZG2L_ADM3_ADSMP_MASK;
-	reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFUALT_SAMPLING);
+	reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFAULT_SAMPLING);
 	rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
 
 exit_hw_init: