[5.10.y-cip,18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC

From: Biju Das <biju.das.jz@bp.renesas.com>
To: Pavel Machek <pavel@denx.de>
Cc: nobuhiro1.iwamatsu@toshiba.co.jp,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	cip-dev@lists.cip-project.org
Subject: [PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document
 RZ/V2L SoC
Date: Tue,  2 Aug 2022 12:08:44 +0100
Message-Id: <20220802110850.1496057-19-biju.das.jz@bp.renesas.com>
In-Reply-To: <20220802110850.1496057-1-biju.das.jz@bp.renesas.com>
References: <20220802110850.1496057-1-biju.das.jz@bp.renesas.com>
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Message ID	20220802110850.1496057-19-biju.das.jz@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Pavel Machek
Headers	show Return-Path: <biju.das.jz@bp.renesas.com> ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) From: Biju Das <biju.das.jz@bp.renesas.com> To: Pavel Machek <pavel@denx.de> Cc: nobuhiro1.iwamatsu@toshiba.co.jp, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, cip-dev@lists.cip-project.org Subject: [PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC Date: Tue, 2 Aug 2022 12:08:44 +0100 Message-Id: <20220802110850.1496057-19-biju.das.jz@bp.renesas.com> In-Reply-To: <20220802110850.1496057-1-biju.das.jz@bp.renesas.com> References: <20220802110850.1496057-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add RZ/{G2LC, V2L} support \| expand [5.10.y-cip,00/24] Add RZ/{G2LC, V2L} support [5.10.y-cip,01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC [5.10.y-cip,02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK [5.10.y-cip,03/24] arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform [5.10.y-cip,04/24] arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform [5.10.y-cip,05/24] clk: renesas: r9a07g044: Add mux and divider for G clock [5.10.y-cip,06/24] clk: renesas: r9a07g044: Add GPU clock and reset entries [5.10.y-cip,07/24] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 [5.10.y-cip,08/24] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions [5.10.y-cip,09/24] dt-bindings: clock: renesas: Document RZ/V2L SoC [5.10.y-cip,10/24] clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC [5.10.y-cip,11/24] clk: renesas: rzg2l: Remove unused notifiers [5.10.y-cip,12/24] clk: renesas: rzg2l: Simplify multiplication/shift logic [5.10.y-cip,13/24] dt-bindings: serial: renesas,scif: Document RZ/V2L SoC [5.10.y-cip,14/24] dt-bindings: serial: renesas,sci: Document RZ/V2L SoC [5.10.y-cip,15/24] dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl [5.10.y-cip,16/24] pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled [5.10.y-cip,17/24] pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register() [5.10.y-cip,18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC [5.10.y-cip,19/24] arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC [5.10.y-cip,20/24] arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK [5.10.y-cip,21/24] arm64: defconfig: Enable ARCH_R9A07G054 [5.10.y-cip,22/24] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file [5.10.y-cip,23/24] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings [5.10.y-cip,24/24] arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board

[5.10.y-cip,18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC

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