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[RFC,06/30] riscv: Kconfig: Enable cpufreq kconfig menu

Message ID	20231220230646.219816-7-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH RFC 06/30] riscv: Kconfig: Enable cpufreq kconfig menu Date: Wed, 20 Dec 2023 23:06:22 +0000 Message-Id: <20231220230646.219816-7-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20231220230646.219816-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20231220230646.219816-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add support for Renesas RZ/Five RISC-V SoC \| expand [RFC,00/30] Add support for Renesas RZ/Five RISC-V SoC [RFC,01/30] arm64: dts: renesas: rzg2ul-smarc: Drop including RZ/G2UL SoM DTSI [RFC,02/30] arm64: dts: renesas: rzg2ul: Move PMOD_SCI0_EN macro to board DTS [RFC,03/30] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS [RFC,04/30] clocksource/drivers/riscv: Increase the clock source rating [RFC,05/30] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback [RFC,06/30] riscv: Kconfig: Enable cpufreq kconfig menu [RFC,07/30] dt-bindings: riscv: Sort the CPU core list alphabetically [RFC,08/30] dt-bindings: riscv: Add Andes AX45MP core to the list [RFC,09/30] riscv: mm: mark noncoherent_supported as __ro_after_init [RFC,10/30] riscv: dma-mapping: only invalidate after DMA, not flush [RFC,11/30] riscv: dma-mapping: skip invalidation before bidirectional DMA [RFC,12/30] riscv: dma-mapping: switch over to generic implementation [RFC,13/30] riscv: asm: vendorid_list: Add Andes Technology to the vendors list [RFC,14/30] riscv: errata: Add Andes alternative ports [RFC,15/30] riscv: mm: dma-noncoherent: nonstandard cache operations support [RFC,16/30] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache c… [RFC,17/30] cache: Add L2 cache management for Andes AX45MP RISC-V core [RFC,18/30] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC [RFC,19/30] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option [RFC,20/30] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC [RFC,21/30] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK [RFC,22/30] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU [RFC,23/30] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C [RFC,24/30] riscv: dts: renesas: rzfive-smarc-som: Enable WDT [RFC,25/30] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes [RFC,26/30] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} [RFC,27/30] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node [RFC,28/30] riscv: dts: renesas: r9a07g043f: Add L2 cache node [RFC,29/30] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property [RFC,30/30] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled

Commit Message

Lad Prabhakar Dec. 20, 2023, 11:06 p.m. UTC

commit effae0e3d9e1139d583e9b5d050f4f948825b8a3 upstream.

Enable cpufreq kconfig menu for RISC-V.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/riscv/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8e4338a21674..c4f576571671 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -720,6 +720,8 @@  menu "CPU Power Management"
 
 source "drivers/cpuidle/Kconfig"
 
+source "drivers/cpufreq/Kconfig"
+
 endmenu # "CPU Power Management"
 
 source "arch/riscv/kvm/Kconfig"