diff mbox series

[6.1.y-cip,2/6] clk: versaclock3: Update vc3_get_div() to avoid divide by zero

Message ID 20240202113754.202827-3-biju.das.jz@bp.renesas.com (mailing list archive)
State Accepted
Headers show
Series Versa3 clk driver improvements | expand

Commit Message

Biju Das Feb. 2, 2024, 11:37 a.m. UTC 
commit eb16ddb838dd8602961b5fc17d1350cd41ae69e0 upstream.

Update vc3_get_div() to avoid divide by zero operation on
vc3_div_round_rate() by returning1, if there is no table match
found.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/clk-versaclock3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
index 880702f6a171..2aa5f5f34ddd 100644
--- a/drivers/clk/clk-versaclock3.c
+++ b/drivers/clk/clk-versaclock3.c
@@ -477,7 +477,7 @@  static unsigned int vc3_get_div(const struct clk_div_table *table,
 		if (clkt->val == val)
 			return clkt->div;
 
-	return 0;
+	return 1;
 }
 
 static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,