[5.10.y-cip,27/36] arm64: dts: renesas: r9a07g043u: Add IRQC node

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Claudiu <claudiu.beznea@tuxon.dev>
To: nobuhiro1.iwamatsu@toshiba.co.jp,
	pavel@denx.de
Cc: cip-dev@lists.cip-project.org,
	biju.das.jz@bp.renesas.com,
	prabhakar.mahadev-lad.rj@bp.renesas.com,
	claudiu.beznea@tuxon.dev
Subject: [PATCH 5.10.y-cip 27/36] arm64: dts: renesas: r9a07g043u: Add IRQC
 node
Date: Wed, 27 Mar 2024 10:17:47 +0200
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Message ID	20240327081756.2228036-28-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
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Headers	show Return-Path: <yoshitake.kobayashi@toshiba.co.jp> ip: 209.85.128.46, mailfrom: claudiu.beznea@tuxon.dev) From: Claudiu <claudiu.beznea@tuxon.dev> To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 27/36] arm64: dts: renesas: r9a07g043u: Add IRQC node Date: Wed, 27 Mar 2024 10:17:47 +0200 Message-Id: <20240327081756.2228036-28-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add IA55 interrupt controller support \| expand [5.10.y-cip,00/36] Add IA55 interrupt controller support [5.10.y-cip,01/36] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle G… [5.10.y-cip,02/36] pinctrl: renesas: rzg2l: Select GPIOLIB_IRQCHIP and IRQ_DOMAIN_HIERARCHY [5.10.y-cip,03/36] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt [5.10.y-cip,04/36] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts [5.10.y-cip,05/36] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks [5.10.y-cip,06/36] pinctrl: renesas: rzg2l: Use devm_clk_get_enabled() helper [5.10.y-cip,07/36] pinctrl: renesas: rzg2l: Enhance driver to support interrupt affinity setting [5.10.y-cip,08/36] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller [5.10.y-cip,09/36] irqdomain: Make of_phandle_args_to_fwspec() generally available [5.10.y-cip,10/36] of: platform: Skip populating IRQ to device resource table [5.10.y-cip,11/36] irqchip: Add RZ/G2L IA55 Interrupt Controller driver [5.10.y-cip,12/36] irqchip: remove MODULE_LICENSE in non-modules [5.10.y-cip,13/36] irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source [5.10.y-cip,14/36] irqchip/renesas-rzg2l: Convert to irq_data_get_irq_chip_data() [5.10.y-cip,15/36] irqchip/renesas-rzg2l: Enhance driver to support interrupt affinity setting [5.10.y-cip,16/36] irqchip/renesas-rzg2l: Use tabs instead of spaces [5.10.y-cip,17/36] irqchip/renesas-rzg2l: Align struct member names to tabs [5.10.y-cip,18/36] irqchip/renesas-rzg2l: Document structure members [5.10.y-cip,19/36] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register [5.10.y-cip,20/36] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on regi… [5.10.y-cip,21/36] irqchip/renesas-rzg2l: Flush posted write in irq_eoi() [5.10.y-cip,22/36] irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() [5.10.y-cip,23/36] irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi() [5.10.y-cip,24/36] irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type [5.10.y-cip,25/36] irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time [5.10.y-cip,26/36] soc: renesas: Kconfig: Enable IRQC driver for RZ/G2L SoC [5.10.y-cip,27/36] arm64: dts: renesas: r9a07g043u: Add IRQC node [5.10.y-cip,28/36] arm64: dts: renesas: r9a07g044: Add IRQC node [5.10.y-cip,29/36] arm64: dts: renesas: r9a07g054: Add IRQC node [5.10.y-cip,30/36] arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts [5.10.y-cip,31/36] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts [5.10.y-cip,32/36] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts [5.10.y-cip,33/36] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts pres… [5.10.y-cip,34/36] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} [5.10.y-cip,35/36] arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 [5.10.y-cip,36/36] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}

[5.10.y-cip,27/36] arm64: dts: renesas: r9a07g043u: Add IRQC node

Commit Message

Patch