[5.10.y-cip,31/53] pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[]

From: Geert Uytterhoeven <geert+renesas@glider.be>

From: Claudiu <claudiu.beznea@tuxon.dev>
To: nobuhiro1.iwamatsu@toshiba.co.jp,
	pavel@denx.de
Cc: cip-dev@lists.cip-project.org,
	biju.das.jz@bp.renesas.com,
	prabhakar.mahadev-lad.rj@bp.renesas.com,
	claudiu.beznea@tuxon.dev
Subject: [PATCH 5.10.y-cip 31/53] pinctrl: renesas: rzg2l: Rename
 rzg2l_gpio_configs[]
Date: Fri, 19 Apr 2024 11:17:20 +0300
Message-Id: <20240419081742.3496709-32-claudiu.beznea.uj@bp.renesas.com>
In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com>
References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com>
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Message ID	20240419081742.3496709-32-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <claudiu.beznea@tuxon.dev> ip: 209.85.218.42, mailfrom: claudiu.beznea@tuxon.dev) From: Claudiu <claudiu.beznea@tuxon.dev> To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 31/53] pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[] Date: Fri, 19 Apr 2024 11:17:20 +0300 Message-Id: <20240419081742.3496709-32-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add initial support for the Renesas RZ/G3S SoC \| expand [5.10.y-cip,00/53] Add initial support for the Renesas RZ/G3S SoC [5.10.y-cip,01/53] clk: renesas: rzg2l: Wait for status bit of SD mux before continuing [5.10.y-cip,02/53] clk: renesas: rzg2l: Lock around writes to mux register [5.10.y-cip,03/53] clk: renesas: rzg2l: Trust value returned by hardware [5.10.y-cip,04/53] clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields [5.10.y-cip,05/53] clk: renesas: rzg2l: Fix computation formula [5.10.y-cip,06/53] clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset() [5.10.y-cip,07/53] clk: renesas: rzg2l: Check reset monitor registers [5.10.y-cip,08/53] dt-bindings: soc: renesas: Document Renesas RZ/G3S SoC variants [5.10.y-cip,09/53] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3S SoC [5.10.y-cip,10/53] clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM [5.10.y-cip,11/53] clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() [5.10.y-cip,12/53] clk: renesas: rzg2l: Use u32 for flag and mux_flags [5.10.y-cip,13/53] clk: renesas: rzg2l: Simplify .determine_rate() [5.10.y-cip,14/53] clk: renesas: rzg2l: Use core->name for clock name [5.10.y-cip,15/53] clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable() [5.10.y-cip,16/53] clk: renesas: rzg2l: Remove critical area [5.10.y-cip,17/53] clk: renesas: rzg2l: Add support for RZ/G3S PLL [5.10.y-cip,18/53] clk: renesas: rzg2l: Add struct clk_hw_data [5.10.y-cip,19/53] clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header [5.10.y-cip,20/53] clk: renesas: rzg2l: Refactor SD mux driver [5.10.y-cip,21/53] clk: divider: Add re-usable determine_rate implementations [5.10.y-cip,22/53] clk: renesas: rzg2l: Add divider clock for RZ/G3S [5.10.y-cip,23/53] dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC [5.10.y-cip,24/53] clk: renesas: Add minimal boot support for RZ/G3S SoC [5.10.y-cip,25/53] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 [5.10.y-cip,26/53] clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux [5.10.y-cip,27/53] soc: renesas: Use "#ifdef" for single-symbol definition checks [5.10.y-cip,28/53] soc: renesas: Identify RZ/G3S SoC [5.10.y-cip,29/53] pinctrl: renesas: rzg2l: Make struct rzg2l_pinctrl_data::dedicated_pins constant [5.10.y-cip,30/53] pinctrl: renesas: rzg2l: Make reverse order of enable() for disable() [5.10.y-cip,31/53] pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[] [5.10.y-cip,32/53] pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() [5.10.y-cip,33/53] pinctrl: renesas: rzg2l: Index all registers based on port offset [5.10.y-cip,34/53] pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets [5.10.y-cip,35/53] pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S [5.10.y-cip,36/53] pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration [5.10.y-cip,37/53] pinctrl: renesas: rzg2l: Add support for different DS values on different groups [5.10.y-cip,38/53] dt-bindings: pinctrl: renesas: Document RZ/G3S SoC [5.10.y-cip,39/53] pinctrl: renesas: rzg2l: Add RZ/G3S support [5.10.y-cip,40/53] dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support [5.10.y-cip,41/53] dt-bindings: serial: renesas,scif: document r9a08g045 support [5.10.y-cip,42/53] dt-bindings: soc: renesas: Document RZ/G3S SMARC SoM [5.10.y-cip,43/53] dt-bindings: soc: renesas: Document SMARC Carrier-II EVK [5.10.y-cip,44/53] arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC [5.10.y-cip,45/53] arm64: dts: renesas: Add initial support for RZ/G3S SMARC SoM [5.10.y-cip,46/53] arm64: dts: renesas: Add initial device tree for RZ SMARC Carrier-II Board [5.10.y-cip,47/53] arm64: dts: renesas: Add initial device tree for RZ/G3S SMARC EVK board [5.10.y-cip,48/53] arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2 [5.10.y-cip,49/53] arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache [5.10.y-cip,50/53] arm64: dts: renesas: rzg3s-smarc-som: Spelling s/device-type/device_type/ [5.10.y-cip,51/53] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 [5.10.y-cip,52/53] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 [5.10.y-cip,53/53] arm64: defconfig: Enable RZ/G3S (R9A08G045) SoC

[5.10.y-cip,31/53] pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[]

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