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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 35/53] pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S Date: Fri, 19 Apr 2024 11:17:24 +0300 Message-Id: <20240419081742.3496709-36-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15622 From: Claudiu Beznea commit 35a3610e5a2407913dd6505de06975ba5056af9e upstream. On RZ/G3S PFC register allow setting 8 functions for individual ports (function1 to function8). For function1 the register need to be configured with 0, for function8 the register need to be configured with 7. We cannot use zero based addressing when requesting functions from different code places as the documentation (RZG3S_pinfunction_List_r1.0.xlsx) states explicitly that function0 is GPIO. Add a new member to struct rzg2l_hwcfg that will keep the offset that needs to be substracted before applying a value to a PFC register. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-17-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index f6a7041028b6..e924bd19ecfb 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -132,9 +132,11 @@ struct rzg2l_register_offsets { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + u8 func_base; }; struct rzg2l_dedicated_configs { @@ -217,6 +219,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int group_selector) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct function_desc *func; unsigned int i, *psel_val; struct group_desc *group; @@ -238,9 +241,9 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i]); + RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]); + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); } return 0;