| Message ID | 20241211181524.28027-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [5.10.y-cip] clk: renesas: rzg2l: Fix FOUTPOSTDIV clk | expand |
Hi! > commit dabf72b85f298970e86891b5218459c17b57b26a upstream. > > While computing foutpostdiv_rate, the value of params->pl5_fracin > is discarded, which results in the wrong refresh rate. Fix the formula > for computing foutpostdiv_rate. Sorry for the delay. This looks okay to me, and I can apply it (*). Best regards, Pavel (*) if it tests ok and nobody raises objections.
Hi all, > -----Original Message----- > From: Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Sent: Thursday, December 12, 2024 3:15 AM > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□ > ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de> > Cc: Biju Das <biju.das.jz@bp.renesas.com> > Subject: [PATCH 5.10.y-cip] clk: renesas: rzg2l: Fix FOUTPOSTDIV clk > > From: Biju Das <biju.das.jz@bp.renesas.com> > > commit dabf72b85f298970e86891b5218459c17b57b26a upstream. > > While computing foutpostdiv_rate, the value of params->pl5_fracin is > discarded, which results in the wrong refresh rate. Fix the formula for > computing foutpostdiv_rate. > > Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support") > Signed-off-by: Hien Huynh <hien.huynh.px@renesas.com> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Link: > https://lore.kernel.org/20241024134236.315289-1-biju.das.jz@bp.renesas.co > m > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > drivers/clk/renesas/rzg2l-cpg.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c > index b1952d2ee8c2..379292eb6fb1 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -556,7 +556,7 @@ static unsigned long > rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, > unsigned long rate) > { > - unsigned long foutpostdiv_rate; > + unsigned long foutpostdiv_rate, foutvco_rate; > > params->pl5_intin = rate / MEGA; > params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA); > @@ -565,10 +565,11 @@ rzg2l_cpg_get_foutpostdiv_rate(struct > rzg2l_pll5_param *params, > params->pl5_postdiv2 = 1; > params->pl5_spread = 0x16; > > - foutpostdiv_rate = > - EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv * > - ((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) > / > - (params->pl5_postdiv1 * params->pl5_postdiv2); > + foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * > MEGA, > + (params->pl5_intin << 24) + > params->pl5_fracin), > + params->pl5_refdiv) >> 24; > + foutpostdiv_rate = DIV_ROUND_CLOSEST_ULL(foutvco_rate, > + params->pl5_postdiv1 * > params->pl5_postdiv2); > > return foutpostdiv_rate; > } > -- > 2.43.0 Sorry for the delay to review and reply. I reviewed this patch, looks good to me. Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Best regards, Nobuhiro
Hi! > Sorry for the delay to review and reply. > I reviewed this patch, looks good to me. > > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Thank you, applied. Best regards, Pavel
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index b1952d2ee8c2..379292eb6fb1 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -556,7 +556,7 @@ static unsigned long rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, unsigned long rate) { - unsigned long foutpostdiv_rate; + unsigned long foutpostdiv_rate, foutvco_rate; params->pl5_intin = rate / MEGA; params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA); @@ -565,10 +565,11 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, params->pl5_postdiv2 = 1; params->pl5_spread = 0x16; - foutpostdiv_rate = - EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv * - ((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) / - (params->pl5_postdiv1 * params->pl5_postdiv2); + foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA, + (params->pl5_intin << 24) + params->pl5_fracin), + params->pl5_refdiv) >> 24; + foutpostdiv_rate = DIV_ROUND_CLOSEST_ULL(foutvco_rate, + params->pl5_postdiv1 * params->pl5_postdiv2); return foutpostdiv_rate; }