[v5.10.y-cip,01/16] clk: Add Sunplus SP7021 clock driver

Commit Message

Claudiu Jan. 22, 2025, 11:52 a.m. UTC

From: Qin Jian <[e-mail]>

commit d54c1fd4a51e8fbc7f9da86b0cd338a4f7cd2bb2 upstream.

Add clock driver for Sunplus SP7021 SoC.

Signed-off-by: Qin Jian <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Stephen Boyd <[e-mail]>
[claudiu.beznea: kept only the code from include/linux/clk-provider.h]
Signed-off-by: Claudiu Beznea <[e-mail]>
---
 include/linux/clk-provider.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Patch

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 75cdef73e751..411f50478043 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -571,6 +571,25 @@  struct clk *clk_register_gate(struct device *dev, const char *name,
 	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
 			       (flags), (reg), (bit_idx),		      \
 			       (clk_gate_flags), (lock))
+/**
+ * devm_clk_hw_register_gate_parent_data - register a gate clock with the
+ * clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_data: parent clk data
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags,  \
+					      reg, bit_idx, clk_gate_flags,   \
+					      lock)                           \
+	__devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL,	      \
+				    (parent_data), (flags), (reg), (bit_idx), \
+				    (clk_gate_flags), (lock))
+
 void clk_unregister_gate(struct clk *clk);
 void clk_hw_unregister_gate(struct clk_hw *hw);
 int clk_gate_is_enabled(struct clk_hw *hw);