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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:25 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 10/14] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Fri, 24 Jan 2025 11:00:01 +0200 Message-ID: <20250124090008.1401077-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17632 From: Claudiu Beznea commit 23c44956bce5aa79c060fc3e5d51843735e6eda6 upstream. Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: the backported patch has references for i2c nodes; the i2c nodes are not available in v6.1 cip, thus fixed conflict by dropping the i2c nodes] Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index f5f3f4f4c8d6..7bc8969a7b5a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -296,4 +308,11 @@ timer { <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; };