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Wed, 12 Mar 2025 11:24:12 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 12/85] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets Date: Wed, 12 Mar 2025 12:21:49 +0100 Message-ID: <20250312112302.1605750-13-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com> References: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com> X-ClientProxiedBy: FR4P281CA0246.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:f5::15) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|OSZPR01MB8767:EE_ X-MS-Office365-Filtering-Correlation-Id: ca9e300c-a801-420a-e6da-08dd61586a05 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|52116014|366016|38350700014; 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Thu, 13 Mar 2025 01:32:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18104 From: Lad Prabhakar commit ee47b94102d2eaed23ac60910003cd0f3fade13c upstream. Add support for the PLLVDO clock and its related CRU clocks and reset entries in the r9a09g057 CPG driver. Introduce `CLK_PLLVDO` and associated clocks like `CLK_PLLVDO_CRU0`, `CLK_PLLVDO_CRU1`, `CLK_PLLVDO_CRU2`, and `CLK_PLLVDO_CRU3`, along with their corresponding dividers. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241202203916.48668-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g057-cpg.c | 45 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 6 ++++ 2 files changed, 51 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 7c4507fd34e6..5aa9710aa402 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -28,6 +28,7 @@ enum clk_ids { CLK_PLLCLN, CLK_PLLDTY, CLK_PLLCA55, + CLK_PLLVDO, /* Internal Core Clocks */ CLK_PLLCM33_DIV16, @@ -35,7 +36,13 @@ enum clk_ids { CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV16, + CLK_PLLVDO_CRU0, + CLK_PLLVDO_CRU1, + CLK_PLLVDO_CRU2, + CLK_PLLVDO_CRU3, /* Module Clocks */ MOD_CLK_BASE, @@ -49,6 +56,12 @@ static const struct clk_div_table dtable_1_8[] = { {0, 0}, }; +static const struct clk_div_table dtable_2_4[] = { + {0, 2}, + {1, 4}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] = { {0, 2}, {1, 4}, @@ -69,6 +82,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), + DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), /* Internal Core Clocks */ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), @@ -78,7 +92,14 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), + DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), + DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), + + DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), + DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), + DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), + DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), @@ -133,6 +154,18 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12), DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13), DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14), + DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18), + DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19), + DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20), + DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21), + DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22), + DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23), + DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24), + DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25), + DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26), + DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27), + DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28), + DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29), }; static const struct rzv2h_reset r9a09g057_resets[] __initconst = { @@ -162,6 +195,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ + DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ + DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ + DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */ + DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */ + DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */ + DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */ + DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */ + DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */ + DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ + DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ + DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ }; const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 0723df4c1134..ed8d2cad3260 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -33,12 +33,18 @@ struct ddiv { #define CPG_CDDIV0 (0x400) #define CPG_CDDIV1 (0x404) +#define CPG_CDDIV3 (0x40C) +#define CPG_CDDIV4 (0x410) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) +#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) +#define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) +#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) +#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) /** * Definitions of CPG Core Clocks