[6.1.y-cip,22/85] arm64: defconfig: Enable R9A09G047 SoC

From: Biju Das <biju.das.jz@bp.renesas.com>

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
CC: Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	tomm.merciai@gmail.com
Subject: [PATCH 6.1.y-cip 22/85] arm64: defconfig: Enable R9A09G047 SoC
Date: Wed, 12 Mar 2025 12:21:59 +0100
Message-ID: <20250312112302.1605750-23-tommaso.merciai.xr@bp.renesas.com>
In-Reply-To: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com>
References: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: 
 UmM2sIgupmLycdXH10EZ86MHREQOeCbZGpJJAtDAatPDJHeDDnDlSplV7IyquANHMoQphaHhZH96ihgXgNsI7vaeGbAlPgCPKz/25Gpcatp25bAwB68XDvAwbojZn/b29WOkNv46letTGWhG6O667XOUVJhQ6xx9uHhepQgUiFDEeCEqLOwxM5csITuDMwcEK2BJ9Ia8gKUGAmX4+OBRDLzqOC6ZdZqd+r5nXFnRXqErIy3HREAzA4dIgbsjLRzShtsyNO8P4wELGLBcuV8Z7ktLZNPBdRQ4fCGGNTdRTkmi9UxBwnBwq/2jq3IObicmGwCN1qUvuIFkNSq19Jp0lFNTdq5TWRYTEzbxpWyMLkSz75COGJhsVObh41AZ1BKOZJMXJkF5rq8cnzQAL/FiRx6mJv1ttvsBzz9h8yueUT3XhKdaa/7XqOX+mP3lISpTK5U/Mu9JynK8dgTPeIIZ9GBs4LtVPh5hwjedTziYmNQvlgu/Tr9qcLhD2GVNwSD+a/XGXlTPHdb/GqV/SkzQXQgnoJUaKxrdZqnrgQvnoAUJgfCpmyVlo6ZNsLw+aPVm9ROQbOkbaO8ydHSlHL2gcJArdI07A0rn3XdjdvTdzDeAX1zYCnd1jt9NVdnwmhdL4euNl5/cotNFC/CC2pRqPlWhG5nP3Wg+MEGzT8qtbyp0VVOBF0diBzKSndFUHK5ABfVcLj596kEIsla1wm0oepk29rHbb+0kUm4PG3v40MpLziEaAozN501UHxJKah92SBjwJoveRyNuP9SO92E26/mSMQcZmdRIvz1mWCSGNYfRXBlwDzsA4EHJ3IskxORcZdLEgJWRD3o0Y/22OucZCcaCq6qQWzvqS+1YsVR1LSZKzboB2oOCyA2NMvbcQh9uzAduTNW5LSDf7Kayf60z0qjEyl7E+jFMCs+yS/s9Y8r+YcovBFn1Cf8r0VIIcgDvXcAoCT9Ovo6zSE7b/EJkQsG/FIZbAk8wWg0fIjjKN9L+9Z6oNIsbafpvnAgQSSuiOfluYByiJOqaxeOWZONFJu7dOvW8KB1RvrUCZPkWbLDOLvnUIoiR2dWwZcs284gqy2F83O8NSzGkwcHurznANH6j1adUDqaLEYncV+iESiRRp0AvNcEld006FL/QGEGqjiYuIVcI4TFulu+vnBVTCdbV3IFgZMxKt69tiZEibtBhcgb8a0b2LWZX9SxbV7lwFQnyZU5K+j900wNva/e6dqRNaZaPmRq4O9KgXnDvmEn4MrkZV+upaS0vQ556Whmv1NjAscMCWsO+2BMJmX5Wq7kOFkkgpQ1D8Qnr/Ay9pmCcTa4khPVxawbjd1UX3K6eCtXYESTktPOnGWpvVeB3MtWOxTgOQboBxyUhpbnxPqHCKa3Ply7dRpf+NgTvrQhPWCC7VSyhFOm9XbVh5MMjVHKcSjZbp86isE0Mm+TrTjaBNLgpUefM5G3kqInAXoFBBaVhtn59R7rTPOcEOVXTjl+Q9rGNvjggIGpd8VJQ5vr7twg/mLMg5UxfH0P6p9X5FwYM8kioOSDk9xNF+PjH7MKWt+GYT6qMWcOoHjzeAzA8BPZmPrJMAnoI7Wa+tMW1sRspKs6j4h9iFo2Ux5IJvAUGphRePCwJIBHlfPgAnls=
X-OriginatorOrg: bp.renesas.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 
 060c3a40-14b5-4e8b-6261-08dd61587b3c
X-MS-Exchange-CrossTenant-AuthSource: OS9PR01MB13950.jpnprd01.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2025 11:24:41.2965
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 53d82571-da19-47e4-9cb4-625a166a4a2a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 
 TSzcZJjtRJC842BN2DBGxTFcthbZestP2ZeqbRx5S7YdZdPJWSkj/PfKF6a3IGUquvSrQXE0JESU8cFEAVntmFoe3iGsj57M4L6fEEnLEKFrhlGmD9Np4NMdkFDBW4F7
X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSCPR01MB12752
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain
List-Id: <cip-dev.lists.cip-project.org>
X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by
 aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for
 <cip-dev@lists.cip-project.org>; Thu, 13 Mar 2025 01:33:05 -0000
X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18115

Message ID	20250312112302.1605750-23-tommaso.merciai.xr@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <yoshitake.kobayashi@toshiba.co.jp> ip: 40.107.74.49, mailfrom: tommaso.merciai.xr@bp.renesas.com) From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> CC: Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 22/85] arm64: defconfig: Enable R9A09G047 SoC Date: Wed, 12 Mar 2025 12:21:59 +0100 Message-ID: <20250312112302.1605750-23-tommaso.merciai.xr@bp.renesas.com> In-Reply-To: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com> References: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain
Series	soc: renesas: Add RZ/G3E support \| expand [6.1.y-cip,00/85] soc: renesas: Add RZ/G3E support [6.1.y-cip,01/85] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants [6.1.y-cip,02/85] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK [6.1.y-cip,03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG [6.1.y-cip,04/85] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG [6.1.y-cip,05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P) [6.1.y-cip,06/85] clk: renesas: Add RZ/V2H(P) CPG driver [6.1.y-cip,07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks [6.1.y-cip,08/85] clk: renesas: rzv2h: Add selective Runtime PM support for clocks [6.1.y-cip,09/85] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT [6.1.y-cip,10/85] clk: renesas: r9a09g057: Add CA55 core clocks [6.1.y-cip,11/85] clk: renesas: r9a09g057: Add clock and reset entries for ICU [6.1.y-cip,12/85] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets [6.1.y-cip,13/85] clk: renesas: rzv2h: Add MSTOP support [6.1.y-cip,14/85] clk: renesas: rzv2h: Add support for RZ/G3E SoC [6.1.y-cip,15/85] clk: renesas: r9a09g047: Add CA55 core clocks [6.1.y-cip,16/85] clk: renesas: r9a09g047: Add I2C clocks/resets [6.1.y-cip,17/85] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC [6.1.y-cip,18/85] arm64: dts: renesas: r9a09g047: Add OPP table [6.1.y-cip,19/85] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM [6.1.y-cip,20/85] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board [6.1.y-cip,21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option [6.1.y-cip,22/85] arm64: defconfig: Enable R9A09G047 SoC [6.1.y-cip,23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H [6.1.y-cip,24/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' pr… [6.1.y-cip,25/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object [6.1.y-cip,26/85] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC [6.1.y-cip,27/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain propert… [6.1.y-cip,28/85] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC [6.1.y-cip,29/85] pinctrl: renesas: rzg2l: Allow more bits for pin configuration [6.1.y-cip,30/85] pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg [6.1.y-cip,31/85] pinctrl: renesas: rzg2l: Enable variable configuration for all [6.1.y-cip,32/85] pinctrl: renesas: rzg2l: Validate power registers for SD and ETH [6.1.y-cip,33/85] pinctrl: renesas: rzg2l: Add function pointer for PFC register locking [6.1.y-cip,34/85] pinctrl: renesas: rzg2l: Add function pointer for PMC register write [6.1.y-cip,35/85] pinctrl: renesas: rzg2l: Add function pointers for OEN register access [6.1.y-cip,36/85] pinctrl: renesas: rzg2l: Add support to configure slew-rate [6.1.y-cip,37/85] pinctrl: renesas: rzg2l: Add support for pull-up/down [6.1.y-cip,38/85] pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_confi… [6.1.y-cip,39/85] pinctrl: renesas: rzg2l: Add support for custom parameters [6.1.y-cip,40/85] pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() [6.1.y-cip,41/85] pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC [6.1.y-cip,42/85] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide [6.1.y-cip,43/85] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) [6.1.y-cip,44/85] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file [6.1.y-cip,45/85] pinctrl: renesas: rzg2l: Reorganize variable configuration macro [6.1.y-cip,46/85] pinctrl: renesas: rzg2l: Clarify OEN read/write support [6.1.y-cip,47/85] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions [6.1.y-cip,48/85] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L [6.1.y-cip,49/85] pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support PIN_CFG_OEN [6.1.y-cip,50/85] pinctrl: renesas: rzg2l: Use dev_err_probe() [6.1.y-cip,51/85] mm/util: Introduce kmemdup_array() [6.1.y-cip,52/85] pinctrl: renesas: Switch to use kmemdup_array() [6.1.y-cip,53/85] pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API [6.1.y-cip,54/85] pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configur… [6.1.y-cip,55/85] pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch… [6.1.y-cip,56/85] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX [6.1.y-cip,57/85] pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() [6.1.y-cip,58/85] pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs [6.1.y-cip,59/85] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger [6.1.y-cip,60/85] pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper [6.1.y-cip,61/85] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table [6.1.y-cip,62/85] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC [6.1.y-cip,63/85] pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E [6.1.y-cip,64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node [6.1.y-cip,65/85] dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end [6.1.y-cip,66/85] dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names' [6.1.y-cip,67/85] dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as required [6.1.y-cip,68/85] dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF sup… [6.1.y-cip,69/85] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif [6.1.y-cip,70/85] serial: sh-sci: describe locking requirements for invalidating RXDMA [6.1.y-cip,71/85] serial: sh-sci: Add support for RZ/V2H(P) SoC [6.1.y-cip,72/85] serial: sh-sci: Use plain struct copy in early_console_setup() [6.1.y-cip,73/85] serial: sh-sci: Check if TX data was written to device in .tx_empty() [6.1.y-cip,74/85] serial: sh-sci: Move runtime PM enable to sci_probe_single() [6.1.y-cip,75/85] serial: sh-sci: Clean sci_ports[0] after at earlycon exit [6.1.y-cip,76/85] serial: sh-sci: Increment the runtime usage counter for the earlycon device [6.1.y-cip,77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol [6.1.y-cip,78/85] dt-bindings: i2c: renesas,riic: Document RZ/Five SoC [6.1.y-cip,79/85] dt-bindings: i2c: renesas,riic: Document R9A09G057 support [6.1.y-cip,80/85] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support [6.1.y-cip,81/85] dt-bindings: i2c: renesas,riic: Document the R9A09G047 support [6.1.y-cip,82/85] i2c: riic: Introduce helper functions for I2C read/write operations [6.1.y-cip,83/85] i2c: riic: Pass register offsets and chip details as OF data [6.1.y-cip,84/85] i2c: riic: Add support for R9A09G057 SoC [6.1.y-cip,85/85] arm64: dts: renesas: r9a09g047: Add I2C nodes

[6.1.y-cip,22/85] arm64: defconfig: Enable R9A09G047 SoC

Commit Message

Patch