[6.1.y-cip,21/21] arm64: defconfig: Enable R9A09G047 SoC

From: Biju Das <biju.das.jz@bp.renesas.com>

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
CC: Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	tomm.merciai@gmail.com
Subject: [PATCH 6.1.y-cip 21/21] arm64: defconfig: Enable R9A09G047 SoC
Date: Fri, 21 Mar 2025 12:00:21 +0100
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Message ID	20250321110021.3612805-22-tommaso.merciai.xr@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <tommaso.merciai.xr@bp.renesas.com> ip: 52.101.228.3, mailfrom: tommaso.merciai.xr@bp.renesas.com) From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> CC: Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 21/21] arm64: defconfig: Enable R9A09G047 SoC Date: Fri, 21 Mar 2025 12:00:21 +0100 Message-ID: <20250321110021.3612805-22-tommaso.merciai.xr@bp.renesas.com> In-Reply-To: <20250321110021.3612805-1-tommaso.merciai.xr@bp.renesas.com> References: <20250321110021.3612805-1-tommaso.merciai.xr@bp.renesas.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain MIME-Version: 1.0
Series	Add support for Renesas RZ/G3E SoC and SMARC-EVK platform \| expand [6.1.y-cip,00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform [6.1.y-cip,01/21] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants [6.1.y-cip,02/21] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK [6.1.y-cip,03/21] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG [6.1.y-cip,04/21] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG [6.1.y-cip,05/21] clk: renesas: Add family-specific clock driver for RZ/V2H(P) [6.1.y-cip,06/21] clk: renesas: Add RZ/V2H(P) CPG driver [6.1.y-cip,07/21] clk: renesas: rzv2h: Add support for dynamic switching divider clocks [6.1.y-cip,08/21] clk: renesas: rzv2h: Add selective Runtime PM support for clocks [6.1.y-cip,09/21] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT [6.1.y-cip,10/21] clk: renesas: r9a09g057: Add CA55 core clocks [6.1.y-cip,11/21] clk: renesas: r9a09g057: Add clock and reset entries for ICU [6.1.y-cip,12/21] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets [6.1.y-cip,13/21] clk: renesas: rzv2h: Add MSTOP support [6.1.y-cip,14/21] clk: renesas: rzv2h: Add support for RZ/G3E SoC [6.1.y-cip,15/21] clk: renesas: r9a09g047: Add CA55 core clocks [6.1.y-cip,16/21] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC [6.1.y-cip,17/21] arm64: dts: renesas: r9a09g047: Add OPP table [6.1.y-cip,18/21] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM [6.1.y-cip,19/21] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board [6.1.y-cip,20/21] soc: renesas: Add RZ/G3E (R9A09G047) config option [6.1.y-cip,21/21] arm64: defconfig: Enable R9A09G047 SoC

[6.1.y-cip,21/21] arm64: defconfig: Enable R9A09G047 SoC

Commit Message

Patch