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[isar-cip-core,11/12] customizations: Mask hvc0 console under qemu-riscv64

Message ID 7dccbac7b8d8b7af7f991c18335b94b0c236a2d8.1664902098.git.jan.kiszka@siemens.com (mailing list archive)
State Handled Elsewhere
Headers show
Series Add qemu-riscv64 target, refactorings, kernel updates, CI fix | expand

Commit Message

Jan Kiszka Oct. 4, 2022, 4:48 p.m. UTC 
From: Jan Kiszka <jan.kiszka@siemens.com>

RISC-V kernels tend to come with a virtual console via SBI. Under QEMU,
this is redundant to the serial console that Linux support as well,
giving two prompts on the UART. Disable the virtual on via systemd.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 recipes-core/customizations/customizations.bb | 8 ++++++++
 1 file changed, 8 insertions(+)
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Patch

diff --git a/recipes-core/customizations/customizations.bb b/recipes-core/customizations/customizations.bb
index 96e88ddb..c057d576 100644
--- a/recipes-core/customizations/customizations.bb
+++ b/recipes-core/customizations/customizations.bb
@@ -12,3 +12,11 @@ 
 require common.inc
 
 DESCRIPTION = "CIP Core image demo & customizations"
+
+do_prepare_build_prepend_qemu-riscv64() {
+	if ! grep -q serial-getty@hvc0.service ${WORKDIR}/postinst; then
+		# suppress SBI console - overlaps with serial console
+		echo >> ${WORKDIR}/postinst
+		echo "systemctl mask serial-getty@hvc0.service" >> ${WORKDIR}/postinst
+	fi
+}