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Mon, 8 Jun 2020 10:33:37 +0000 From: "johnsonch.chen@moxa.com" To: "nobuhiro1.iwamatsu@toshiba.co.jp" , "pavel@denx.de" , "cip-dev@lists.cip-project.org" Subject: [cip-dev] [PATCH 4.4.y-cip 1/3] ARM: dts: am33xx: Added macros for numeric pinmux addresses Thread-Topic: [PATCH 4.4.y-cip 1/3] ARM: dts: am33xx: Added macros for numeric pinmux addresses Thread-Index: AQHWPX0Zto1AlmOWqEKHG+fmEkG11Q== Date: Mon, 8 Jun 2020 10:33:37 +0000 Message-ID: Accept-Language: zh-TW, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [123.51.145.16] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1a0e3b3e-fa12-4f3f-f300-08d80b976744 x-ms-traffictypediagnostic: HK2PR01MB3378: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:97; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: OusSQ9LFRv4D9MyjyQoe/7w/bVEwefbjiJVcTA019nicoBGNjsBnm6LNoXunSR9GwFu8gnB/m9/7jaPIy+Gd9EzoNUgxcEvlDQcgY4lLxSxU74fvUuId3TU6d6VfeMvMitWFAsj6BLcd+dXcfEjG+CSW0LiqH2+gu4Lp7nG88Z4LR8rnpcC9FYfJ5+Mkzs8rVbq9cUvkDuQpyQtyQUgDoSXSbVk4xmXRy9slS/h2xOJLziwCodIR1nkyhNps9MszDJu02L6nLwxRxycZy3NEyHd5Tk0RF7zuRhj4DyHzOCgzU7gItcbINJyEUez2ziETJNlea7sOIPraS/HahBk87w== x-ms-exchange-antispam-messagedata: 2e6vFuIPtc32o0P0l5YFsIYcse7VQM15IS9sR9qf8RpRRxZshFJHxzP6f2k7IwMqUXNhcpnZgnzxU9e7ZzwH1LOWscr5Da0wr7XbtXTZXu9YSckxrANIZu75SmeZRaCh5WMaHZG8AJJYku7iEoa0B933voqBVrLrHpL5FZV8NPK9TOH51UrZ6lbc6oRTsxO5Zeyv2P5YQWBZ4oy7sWx75UfaF0qZSHmpsJKUSmB9U/eIAeW5bqRk0eAmk8mS6RwGTIw32YrKBy5g3ap+ZzV6EW/ynAtsK8GkZfTFLug6SVHlMReOx5RxV8mG7Nj67gq1I75ukYEA0SABSX+Mpl21Li7oc7O+vb8mTgChAG5JEysxITECgd3K+qWaGxFxWXYlJRN5nY7X3NOruBbpZqHq/IjDE4YEqofx/Ayx2LQNwBP91mZ5yMsYlxC9I7Pd4IfUw8ViubRZZGbgq0dAyerDmHNd0h8GGu0wi1m1x+SnABc= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: moxa.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1a0e3b3e-fa12-4f3f-f300-08d80b976744 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jun 2020 10:33:37.1785 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 5571c7d4-286b-47f6-9dd5-0aa688773c8e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DHuUYQE4QinC9l4pxnsoCNL14x3AwXWQ5hflGYcBSPVH08QiJN5r37sRKdbIUvpAPc+VUDsgaNBhrenAehc3og== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2PR01MB3378 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: fZmu93DHgzGjk3IrjuP8ely1x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1591612420; bh=gHtV2JQjd6ejcnbog7cC4WPsNNb2h6Bej2UWqflQoyo=; h=Content-Type:Date:From:Reply-To:Subject:To; b=HcBX1yeGQEyYPFAGhzey5vZKju4vt56rkzV674LuZM2i1yBanoFleEPl0pDlw5X3bcX 8IS3oVJ5lY2PGLYgHGDFx2VKUy/10JPW13dO82WDJhu9OG9rhhM+wDCHi4XFqTrYE2rb1 /3SXWiTtfjnpAWcuSZ0RsmsHbajaSZbpn/E= From: Christina Quast commit 7ebd1ea798a4932231b18499df136fb552f6f648 upstream. The values are extraced from the "AM335x SitaraTM Processors Technical Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the file autogenerated by TI PinMux. Signed-off-by: Christina Quast Reviewed-by: Rob Herring Signed-off-by: Tony Lindgren [Johnson: Add SPDX License] Signed-off-by: Johnson Chen --- include/dt-bindings/pinctrl/am33xx.h | 131 ++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h index 226f77246a70..17877e85980b 100644 --- a/include/dt-bindings/pinctrl/am33xx.h +++ b/include/dt-bindings/pinctrl/am33xx.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants specific to AM33XX pinctrl bindings. */ @@ -39,5 +40,133 @@ #undef PIN_OFF_INPUT_PULLDOWN #undef PIN_OFF_WAKEUPENABLE -#endif +#define AM335X_PIN_OFFSET_MIN 0x0800U + +#define AM335X_PIN_GPMC_AD0 0x800 +#define AM335X_PIN_GPMC_AD1 0x804 +#define AM335X_PIN_GPMC_AD2 0x808 +#define AM335X_PIN_GPMC_AD3 0x80c +#define AM335X_PIN_GPMC_AD4 0x810 +#define AM335X_PIN_GPMC_AD5 0x814 +#define AM335X_PIN_GPMC_AD6 0x818 +#define AM335X_PIN_GPMC_AD7 0x81c +#define AM335X_PIN_GPMC_AD8 0x820 +#define AM335X_PIN_GPMC_AD9 0x824 +#define AM335X_PIN_GPMC_AD10 0x828 +#define AM335X_PIN_GPMC_AD11 0x82c +#define AM335X_PIN_GPMC_AD12 0x830 +#define AM335X_PIN_GPMC_AD13 0x834 +#define AM335X_PIN_GPMC_AD14 0x838 +#define AM335X_PIN_GPMC_AD15 0x83c +#define AM335X_PIN_GPMC_A0 0x840 +#define AM335X_PIN_GPMC_A1 0x844 +#define AM335X_PIN_GPMC_A2 0x848 +#define AM335X_PIN_GPMC_A3 0x84c +#define AM335X_PIN_GPMC_A4 0x850 +#define AM335X_PIN_GPMC_A5 0x854 +#define AM335X_PIN_GPMC_A6 0x858 +#define AM335X_PIN_GPMC_A7 0x85c +#define AM335X_PIN_GPMC_A8 0x860 +#define AM335X_PIN_GPMC_A9 0x864 +#define AM335X_PIN_GPMC_A10 0x868 +#define AM335X_PIN_GPMC_A11 0x86c +#define AM335X_PIN_GPMC_WAIT0 0x870 +#define AM335X_PIN_GPMC_WPN 0x874 +#define AM335X_PIN_GPMC_BEN1 0x878 +#define AM335X_PIN_GPMC_CSN0 0x87c +#define AM335X_PIN_GPMC_CSN1 0x880 +#define AM335X_PIN_GPMC_CSN2 0x884 +#define AM335X_PIN_GPMC_CSN3 0x888 +#define AM335X_PIN_GPMC_CLK 0x88c +#define AM335X_PIN_GPMC_ADVN_ALE 0x890 +#define AM335X_PIN_GPMC_OEN_REN 0x894 +#define AM335X_PIN_GPMC_WEN 0x898 +#define AM335X_PIN_GPMC_BEN0_CLE 0x89c +#define AM335X_PIN_LCD_DATA0 0x8a0 +#define AM335X_PIN_LCD_DATA1 0x8a4 +#define AM335X_PIN_LCD_DATA2 0x8a8 +#define AM335X_PIN_LCD_DATA3 0x8ac +#define AM335X_PIN_LCD_DATA4 0x8b0 +#define AM335X_PIN_LCD_DATA5 0x8b4 +#define AM335X_PIN_LCD_DATA6 0x8b8 +#define AM335X_PIN_LCD_DATA7 0x8bc +#define AM335X_PIN_LCD_DATA8 0x8c0 +#define AM335X_PIN_LCD_DATA9 0x8c4 +#define AM335X_PIN_LCD_DATA10 0x8c8 +#define AM335X_PIN_LCD_DATA11 0x8cc +#define AM335X_PIN_LCD_DATA12 0x8d0 +#define AM335X_PIN_LCD_DATA13 0x8d4 +#define AM335X_PIN_LCD_DATA14 0x8d8 +#define AM335X_PIN_LCD_DATA15 0x8dc +#define AM335X_PIN_LCD_VSYNC 0x8e0 +#define AM335X_PIN_LCD_HSYNC 0x8e4 +#define AM335X_PIN_LCD_PCLK 0x8e8 +#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec +#define AM335X_PIN_MMC0_DAT3 0x8f0 +#define AM335X_PIN_MMC0_DAT2 0x8f4 +#define AM335X_PIN_MMC0_DAT1 0x8f8 +#define AM335X_PIN_MMC0_DAT0 0x8fc +#define AM335X_PIN_MMC0_CLK 0x900 +#define AM335X_PIN_MMC0_CMD 0x904 +#define AM335X_PIN_MII1_COL 0x908 +#define AM335X_PIN_MII1_CRS 0x90c +#define AM335X_PIN_MII1_RX_ER 0x910 +#define AM335X_PIN_MII1_TX_EN 0x914 +#define AM335X_PIN_MII1_RX_DV 0x918 +#define AM335X_PIN_MII1_TXD3 0x91c +#define AM335X_PIN_MII1_TXD2 0x920 +#define AM335X_PIN_MII1_TXD1 0x924 +#define AM335X_PIN_MII1_TXD0 0x928 +#define AM335X_PIN_MII1_TX_CLK 0x92c +#define AM335X_PIN_MII1_RX_CLK 0x930 +#define AM335X_PIN_MII1_RXD3 0x934 +#define AM335X_PIN_MII1_RXD2 0x938 +#define AM335X_PIN_MII1_RXD1 0x93c +#define AM335X_PIN_MII1_RXD0 0x940 +#define AM335X_PIN_RMII1_REF_CLK 0x944 +#define AM335X_PIN_MDIO 0x948 +#define AM335X_PIN_MDC 0x94c +#define AM335X_PIN_SPI0_SCLK 0x950 +#define AM335X_PIN_SPI0_D0 0x954 +#define AM335X_PIN_SPI0_D1 0x958 +#define AM335X_PIN_SPI0_CS0 0x95c +#define AM335X_PIN_SPI0_CS1 0x960 +#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 +#define AM335X_PIN_UART0_CTSN 0x968 +#define AM335X_PIN_UART0_RTSN 0x96c +#define AM335X_PIN_UART0_RXD 0x970 +#define AM335X_PIN_UART0_TXD 0x974 +#define AM335X_PIN_UART1_CTSN 0x978 +#define AM335X_PIN_UART1_RTSN 0x97c +#define AM335X_PIN_UART1_RXD 0x980 +#define AM335X_PIN_UART1_TXD 0x984 +#define AM335X_PIN_I2C0_SDA 0x988 +#define AM335X_PIN_I2C0_SCL 0x98c +#define AM335X_PIN_MCASP0_ACLKX 0x990 +#define AM335X_PIN_MCASP0_FSX 0x994 +#define AM335X_PIN_MCASP0_AXR0 0x998 +#define AM335X_PIN_MCASP0_AHCLKR 0x99c +#define AM335X_PIN_MCASP0_ACLKR 0x9a0 +#define AM335X_PIN_MCASP0_FSR 0x9a4 +#define AM335X_PIN_MCASP0_AXR1 0x9a8 +#define AM335X_PIN_MCASP0_AHCLKX 0x9ac +#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 +#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 +#define AM335X_PIN_WARMRSTN 0x9b8 +#define AM335X_PIN_NNMI 0x9c0 +#define AM335X_PIN_TMS 0x9d0 +#define AM335X_PIN_TDI 0x9d4 +#define AM335X_PIN_TDO 0x9d8 +#define AM335X_PIN_TCK 0x9dc +#define AM335X_PIN_TRSTN 0x9e0 +#define AM335X_PIN_EMU0 0x9e4 +#define AM335X_PIN_EMU1 0x9e8 +#define AM335X_PIN_RTC_PWRONRSTN 0x9f8 +#define AM335X_PIN_PMIC_POWER_EN 0x9fc +#define AM335X_PIN_EXT_WAKEUP 0xa00 +#define AM335X_PIN_USB0_DRVVBUS 0xa1c +#define AM335X_PIN_USB1_DRVVBUS 0xa34 +#define AM335X_PIN_OFFSET_MAX 0x0a34U + +#endif