mbox series

[v2,0/3] CXL Region Provisioning Fixes

Message ID 165973125417.1526540.14425647258796609596.stgit@dwillia2-xfh.jf.intel.com
Headers show
Series CXL Region Provisioning Fixes | expand

Message

Dan Williams Aug. 5, 2022, 8:27 p.m. UTC 
Changes and new fixes since v1 [1]:

While reviewing "cxl/region: Constrain region granularity scaling
factor" [2] it became clear that the attempt to support region granularity >
window (ACPI CFMWS entry) granularity was misguided. Update the
implementation to disallow that configuration, but also allow
unrestricted granularity settings when the window interleave-ways is 1.

Speaking of window interleave-ways == 1 add a fix to
cxl_port_setup_targets() for the case where it does not need to assign
addition address bits to the decode.

Lastly, fix a regression with the original version of "cxl/region: Move
HPA setup to cxl_region_attach()" that broke the establishment of
->hpa_range in switch decoders.

An expansion of cxl_test to backstop these fixes will be posted shortly.

These are based on the updated state of the cxl/pending branch that has
pulled in the reviewed fixes from Dan and Bagas.

[1]: https://lore.kernel.org/r/165853775181.2430596.3054032756974329979.stgit@dwillia2-xfh.jf.intel.com/
[2]: https://lore.kernel.org/r/165853778028.2430596.7493880465382850752.stgit@dwillia2-xfh.jf.intel.com/

---

Dan Williams (3):
      cxl/region: Move HPA setup to cxl_region_attach()
      cxl/region: Fix x1 interleave to greater than x1 interleave routing
      cxl/region: Disallow region granularity != window granularity


 drivers/cxl/core/hdm.c    |   26 ++------------------------
 drivers/cxl/core/region.c |   43 ++++++++++++++++++++++++++++++++++---------
 2 files changed, 36 insertions(+), 33 deletions(-)

base-commit: 2901c8bdedca19e5efdab2ea55b465102231b315