[v5,0/6] Add sanity check for interleave setup

Message

Dave Jiang Aug. 25, 2022, 4:07 p.m. UTC

The small series adds sanity check for the combination of interleave ways
and interleave granularity during region and port configuration. The
calculation references CXL spec 3.0 8.2.4.19.13 implementation note #3. The
checks also added HDM CAP retrieval for the support of new interleave ways
where 3, 6, and 12 ways support as well as 16 ways support.

v5:
- Various spelling errors (Jonathan)
- Make "CXL spec rev3.0" changes throughout to be consistent (Jonathan)
- Change CXL_HDM_INTERLEAVE_CAP_DEFAULT to CXL_HDM_INTERLEAVE_CAP_BASELINE
  (Jonathan)
- Fix up commit header in reference to cxl_interleave_verify() to
  cxl_interleave_capable() (Jonathan)
- Move dev_set_drvdata() for cxl_test to first patch (Jonathan)

v4:
- Add documentation for sysfs entries (Dan)
- Remove unneeded checks for drvdata validity (Dan)
- Add renaming of cxl_port_attribute_groups to cxl_port_dynamic_attr_groups
  (Dan)

  v3:
  - Move cxl_interleave_capable() to core/region.c. (Dan)
  - Open code verify of interleave ways against cap mask. (Dan)

  v2:
  - Change cxl_interleave_verify() to cxl_interleave_capable(). (Dan)
  - Move error output inside verify function. (Dan)
  - Remove unneeded enums. (Dan)
  - Use is_power_of_2() to detect encoded interleave ways. (Dan)
  - Change iw to eiw and ig to eig for encoded values. (Alison)
  - Change interleave capabilities to mask for easier comparison. (Dan)
  - Change valid_interleave() to valid_interleave_ways()
  - Add setting fo interleave_cap to cxl_test. (Dan)

---

Dave Jiang (6):
      cxl: Add check for result of interleave ways plus granularity combo
      cxl: Add CXL spec v3.0 interleave support
      tools/testing/cxl: Add interleave check support to mock cxl port device
      cxl: change cxl_port_attribute_groups naming to avoid confusion
      cxl: export interleave address mask as port sysfs attribute
      cxl: export intereleave capability as port sysfs attribute


 Documentation/ABI/testing/sysfs-bus-cxl | 24 ++++++++++++
 drivers/cxl/core/hdm.c                  |  6 +++
 drivers/cxl/core/region.c               | 50 ++++++++++++++++++++++++-
 drivers/cxl/cxl.h                       |  2 +
 drivers/cxl/cxlmem.h                    |  5 +++
 drivers/cxl/port.c                      | 33 +++++++++++++++-
 tools/testing/cxl/test/cxl.c            |  3 ++
 7 files changed, 120 insertions(+), 3 deletions(-)

base-commit: 1cd8a2537eb07751d405ab7e2223f20338a90506
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