[0/4] cxl: DPA partition metadata is a mess...

Message

Dan Williams Jan. 17, 2025, 6:10 a.m. UTC

As noted in patch3, the pending efforts to add CXL Accelerator (type-2)
device [1], and Dynamic Capacity (DCD) support [2], tripped on the
no-longer-fit-for-purpose design in the CXL subsystem for tracking
device-physical-address (DPA) metadata.

In fact there was no design at all, just a couple of open-coded 'struct
resource' instances for 'ram' and 'pmem' and a pile of explicit code
referencing those resources directly.

See patch3 for more details on the specific problems that caused, and
patch4 for the eyesore reduction of making the DPA allocation algorithm
partition number agnostic.

The motivation with this effort is to make it easier to land the Type-2
and DCD series.

Next on the cleanup list is 'enum cxl_decoder_mode' which has little to
exist after partition info is centralized. That cleanup is left as an
exercise for the DCD series.

This series passes a cxl-test run at every patch.

[1]: http://lore.kernel.org/[e-mail]
[2]: http://lore.kernel.org/[e-mail]

---

Dan Williams (4):
      cxl: Remove the CXL_DECODER_MIXED mistake
      cxl: Introduce to_{ram,pmem}_{res,perf}() helpers
      cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info'
      cxl: Make cxl_dpa_alloc() DPA partition number agnostic


 drivers/cxl/core/cdat.c      |   63 ++++++-----
 drivers/cxl/core/hdm.c       |  244 +++++++++++++++++++++++++++++++++---------
 drivers/cxl/core/mbox.c      |   84 ++++++--------
 drivers/cxl/core/memdev.c    |   42 ++++---
 drivers/cxl/core/region.c    |   22 +---
 drivers/cxl/cxl.h            |    4 -
 drivers/cxl/cxlmem.h         |   94 ++++++++++++++--
 drivers/cxl/mem.c            |    2 
 drivers/cxl/pci.c            |    7 +
 tools/testing/cxl/test/cxl.c |   22 ++--
 tools/testing/cxl/test/mem.c |    7 +
 11 files changed, 396 insertions(+), 195 deletions(-)

base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4