[0/9] CXL port prep work

Message

Ben Widawsky Nov. 29, 2021, 9:47 p.m. UTC

These are the first several patches from the CXL port patch series. They
primarily rework handling some of the handling in cxl_pci reworks and puts some
infrastructure in place for endpoints and ports.

The patches do not have overlap with other domains, such as PCI.

Ben Widawsky (9):
  cxl: Rename CXL_MEM to CXL_PCI
  cxl: Flesh out register names
  cxl/pci: Extract device status check
  cxl/pci: Implement Interface Ready Timeout
  cxl/pci: Don't poll doorbell for mailbox access
  cxl/pci: Add new DVSEC definitions
  cxl/acpi: Map component registers for Root Ports
  cxl: Introduce module_cxl_driver
  cxl/core: Convert decoder range to resource

 drivers/cxl/Kconfig     |  23 +++---
 drivers/cxl/Makefile    |   2 +-
 drivers/cxl/acpi.c      |  35 ++++-----
 drivers/cxl/core/bus.c  |  23 +++++-
 drivers/cxl/core/regs.c |  54 ++++++++++++++
 drivers/cxl/cxl.h       |  15 +++-
 drivers/cxl/pci.c       | 152 +++++++++++++++-------------------------
 drivers/cxl/pci.h       |  41 ++++++++---
 8 files changed, 211 insertions(+), 134 deletions(-)