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(unknown [104.36.25.245]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a254.dreamhost.com (Postfix) with ESMTPSA id 4LyxBW51LCz2t; Wed, 3 Aug 2022 21:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1659588660; bh=iCmPQoYRvy04G/hCSh521jn34l0VwQZYcXz6/uc2hjg=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=fxhygYR52m8OLblEPBjVczxowbeBvJy7GF12yTgCizN4IgGOcQZfd5Xhr/EeGQrnH B+YXMVOKIT3PhfeJaZgEMUPpxLOE5F4HDL1zBOPfaaFY+QUPwbl7ktZJ7/ws9x9zLo VyymOlb3cOmCH0OZapgthR3TlUnQ+Le9GRXl/cvPJT9uH+UCex2/VXAaOY7PcpNMYv 1XMy3no+XPX41TCy24lpsy3/VgLjpcwUSa6VNzMv7mvkYO+UI5gNASRYLj3C6ZJotZ Nv7gBjgmK03LWEmx2pFJLrEkNOjQD16Qx9h+oLMFCEORtG39B6o3HTw+ENYBGqV7kS D0ZrWa3Zt0Xiw== From: Davidlohr Bueso To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, bwidawsk@kernel.org, Jonathan.Cameron@huawei.com, ira.weiny@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, a.manzanares@samsung.com, mcgrof@kernel.org, dave@stgolabs.net, linux-kernel@vger.kernel.org Subject: [RFC PATCH 0/2] cxl: BG operations and device sanitation Date: Wed, 3 Aug 2022 21:50:27 -0700 Message-Id: <20220804045029.2905056-1-dave@stgolabs.net> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Hello, The following is a followup to some of the discussions around CXL device security and sanitation[0, 1]. It is marked as RFC mostly to see if the background handling will satisfy all users, not just sanitize/overwrite. For example there has been ideas to avoid command hogging the device and/or interleaving scan media regions instead of all in one, etc. More details in each patch, but: Patch 1 adds the required background cmd handling bits. While this is currently only polling, it would be good to know if there are any fundamental blockers for supporting irqs (beyond just background ops) between PCIe and CXL. For example, are there any requirements/difficulties that is not the standard MSI/MSI-X PCI vector allocation + devm_request_irq()? I have not looked at this into details but it the topic has come up in the past as delicate', iirc. Patch 2 implements the sanitation commands (overwrite and secure erase). As for testing, while I used the mock device to test the secure erase command, I ended up hacking up a prototype[2] for qemu to support overwrite and bg commands. So while the some of the paths this series introduces have been exercised, there is of course a lot more to do. Applies against Dave's cxl-security branch[2] which deals with the pmem-only bits. Thanks, Davidlohr [0]: https://lore.kernel.org/all/20220708172455.gi37dh3od4w5lqrd@offworld/ [1]: https://lore.kernel.org/all/165791918718.2491387.4203738301057301285.stgit@djiang5-desk3.ch.intel.com/ [2]: https://github.com/davidlohr/qemu/commit/64a93a5b824b59d3b547f06f7fbb1269fb4790ce [3]: https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/log/?h=cxl-security Davidlohr Bueso (2): cxl/mbox: Add background operation handling machinery cxl/mem: Support sanitation commands Documentation/ABI/testing/sysfs-bus-cxl | 19 ++ drivers/cxl/core/core.h | 2 +- drivers/cxl/core/mbox.c | 304 +++++++++++++++++++++++- drivers/cxl/core/memdev.c | 58 +++++ drivers/cxl/core/port.c | 9 +- drivers/cxl/cxl.h | 8 + drivers/cxl/cxlmem.h | 65 ++++- drivers/cxl/pci.c | 3 +- drivers/cxl/pmem.c | 5 +- drivers/cxl/security.c | 13 +- include/uapi/linux/cxl_mem.h | 2 + 11 files changed, 461 insertions(+), 27 deletions(-) --- 2.37.1