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Tue, 11 Apr 2023 18:03:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT072.mail.protection.outlook.com (10.13.176.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6298.28 via Frontend Transport; Tue, 11 Apr 2023 18:03:11 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 11 Apr 2023 13:03:10 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v3 0/6] cxl/pci: Add support for RCH RAS error handling Date: Tue, 11 Apr 2023 13:02:56 -0500 Message-ID: <20230411180302.2678736-1-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT072:EE_|CY8PR12MB8242:EE_ X-MS-Office365-Filtering-Correlation-Id: d0c69dd7-40b5-4150-b938-08db3ab70394 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2023 18:03:11.6092 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0c69dd7-40b5-4150-b938-08db3ab70394 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8242 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org This patchset adds error handling support for restricted CXL host (RCH) downstream ports. This is necessary because RCH downstream ports are implemented in RCRBs and report protocol errors through a root complex event collector (RCEC). The RCH error reporting flow is not currently supported by the CXL driver and will be added by this patchset. The first patch discovers the RCH dport AER and RAS registers. These will be mapped later and used in CXL driver error logging. The second patch exports cper_mem_err_unpack(). cper_mem_err_unpack() is a dependency for using the cper_print_aer() AER trace logging. The third patch exports cper_print_aer(). cper_print_aer() is used for CXL AER error logging because it provides a common format for logging into dmesg. The fourth patch maps the AER and RAS registers. This patch also adds the RCH handler for logging downstream port AER and RAS information. The fifth patch is AER port driver changes forwarding RCH errors to the RCiEP RCH handler. The sixth patch enables internal AER errors for RCEC's with CXL RCiEPs. The CONFIG_PCIEAER_CXL kernel option is introduced to enable this logic. Changes in V3: - Correct base commit in cover sheet. - Change hardcoded return 0 to NULL in regs.c. - Remove calls to pci_disable_pcie_error_reporting(pdev) and pci_enable_pcie_error_reporting(pdev) in mem.c; - Move RCEC interrupt unmask to PCIe port AER driver's probe. - Fixes missing PCIEAER and PCIEPORTBUS config option error. - Rename cxl_rcrb_setup() to cxl_setup_rcrb() in mem.c. - Update cper_mem_err_unpack() patch subject and description. Changes in V2: - Refactor RCH initialization into cxl_mem driver. - Includes RCH RAS and AER register discovery and mapping. - Add RCEC protocol error interrupt forwarding to CXL endpoint handler. - Change AER and RAS logging to use existing trace routines. - Enable RCEC AER internal errors. Robert Richter (2): PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman (4): cxl/pci: Add RCH downstream port AER and RAS register discovery efi/cper: Export cper_mem_err_unpack() for use by modules PCI/AER: Export cper_print_aer() for use by modules cxl/pci: Add RCH downstream port error logging drivers/cxl/core/pci.c | 126 +++++++++++++++++++++++++++++---- drivers/cxl/core/regs.c | 94 +++++++++++++++++++++---- drivers/cxl/cxl.h | 18 +++++ drivers/cxl/mem.c | 110 ++++++++++++++++++++++++++--- drivers/firmware/efi/cper.c | 1 + drivers/pci/pcie/Kconfig | 8 +++ drivers/pci/pcie/aer.c | 135 ++++++++++++++++++++++++++++++++++++ 7 files changed, 457 insertions(+), 35 deletions(-) base-commit: ca712e47054678c5ce93a0e0f686353ad5561195