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Tue, 23 May 2023 23:23:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT041.mail.protection.outlook.com (10.13.174.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.29 via Frontend Transport; Tue, 23 May 2023 23:23:01 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 23 May 2023 18:22:59 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling Date: Tue, 23 May 2023 18:21:51 -0500 Message-ID: <20230523232214.55282-1-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT041:EE_|PH7PR12MB7259:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b982afc-c75b-4396-f341-08db5be4a71e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 23:23:01.6145 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b982afc-c75b-4396-f341-08db5be4a71e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7259 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Patches #1 to #16 are a rework of the Component Register setup. This is needed to share multiple CXL capabilities (HDM and RAS) for the same component, also there can be different components implementing the same capability, finally RCH mode should be supported too. The general approach to solve this is to: * Unify code for components and capabilities in VH and RCH modes. * Early setup of the Component Register base address. * Create and store the register mappings to later use it for mapping the capability I/O ranges. Patches #17 to #23 enable CXL RCH error handling. These are needed because RCH downstream port protocol error handling is implemented uniquely and not currently supported. These patches address the following: * Discovery and mapping of RCH downstream port AER registers. * AER portdrv changes to support CXL RCH protocol errors. * Interrupt setup specific to RCH mode: enabling RCEC internal errors and disabling root port interrupts. Dan Williams (1): cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Robert Richter (16): cxl/acpi: Probe RCRB later during RCH downstream port creation cxl: Rename member @dport of struct cxl_dport to @dev cxl/core/regs: Add @dev to cxl_register_map cxl/acpi: Moving add_host_bridge_uport() around cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port cxl/regs: Remove early capability checks in Component Register setup cxl/pci: Early setup RCH dport component registers from RCRB cxl/port: Store the port's Component Register mappings in struct cxl_port cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state cxl/hdm: Use stored Component Register mappings to map HDM decoder capability cxl/port: Remove Component Register base address from struct cxl_port cxl/port: Remove Component Register base address from struct cxl_dport cxl/pci: Remove Component Register base address from struct cxl_dev_state PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman (6): cxl/pci: Refactor component register discovery for reuse cxl/pci: Add RCH downstream port AER register discovery PCI/AER: Refactor cper_print_aer() for use by CXL driver module cxl/pci: Update CXL error logging to use RAS register address cxl/pci: Prepare for logging RCH downstream port protocol errors cxl/pci: Add RCH downstream port error logging base-commit: a70fc4ed20a6118837b0aecbbf789074935f473b drivers/cxl/acpi.c | 191 +++++++++++++++++++--------------- drivers/cxl/core/hdm.c | 59 +++++------ drivers/cxl/core/pci.c | 140 ++++++++++++++++++++++--- drivers/cxl/core/port.c | 157 ++++++++++++++++++++++++---- drivers/cxl/core/region.c | 4 +- drivers/cxl/core/regs.c | 152 ++++++++++++++++++++++++--- drivers/cxl/cxl.h | 56 ++++++---- drivers/cxl/cxlmem.h | 5 +- drivers/cxl/mem.c | 16 +-- drivers/cxl/pci.c | 109 +++++++------------ drivers/cxl/port.c | 5 +- drivers/pci/pcie/Kconfig | 12 +++ drivers/pci/pcie/aer.c | 173 ++++++++++++++++++++++++++++-- include/linux/aer.h | 2 +- tools/testing/cxl/Kbuild | 2 +- tools/testing/cxl/test/cxl.c | 10 +- tools/testing/cxl/test/mock.c | 12 +-- tools/testing/cxl/test/mock.h | 7 +- 18 files changed, 824 insertions(+), 288 deletions(-)