[v4,0/2] cxl/region: add interleave capability check

Message

Xingtao Yao (Fujitsu) April 22, 2024, 9:13 a.m. UTC

Changes:
v3 -> v4:
1. modify variable naming. (Jonathan)
2. add a comment with a specification reference for the interleave bits
   mathematical calculation formula. (Jonathan)
3. add some descriptions about the changes in comment. (Fan)
4. add passthrough flag to struct cxl_switch_decoder. (newly added)

Currently driver does not check the interleave capability of target, it
can attach target to region even if target does not support the interleave
capability. Thus, applications access the memory will occur unexpected
behavior, such as segmentation fault.

Therefore, it is necessary to check the interleave capability of target
before attaching it to region. If the check fails, the attachment
operation should be stopped.

Since the host-bridges with single port and switches with single dport
do not contain one instance of the CXL HDM Decoder Capability Structure,
the above check does not apply to them, driver should skip this pattern.
So when implementing the patch 2, the patch 1 is needed.

Yao Xingtao (2):
  cxl/core: add passthrough flag to struct cxl_switch_decoder
  cxl/region: check interleave capability

 drivers/cxl/core/hdm.c    |  6 ++++
 drivers/cxl/core/region.c | 70 +++++++++++++++++++++++++++++++++++++++
 drivers/cxl/cxl.h         |  4 +++
 drivers/cxl/cxlmem.h      |  1 +
 4 files changed, 81 insertions(+)