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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF000023DA.mail.protection.outlook.com (10.167.244.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.5 via Frontend Transport; Mon, 15 Jul 2024 17:28:43 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 15 Jul 2024 12:28:42 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Mon, 15 Jul 2024 12:28:41 -0500 From: To: , , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v2 00/15] cxl: add Type2 device support Date: Mon, 15 Jul 2024 18:28:20 +0100 Message-ID: <20240715172835.24757-1-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alejandro.lucero-palau@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023DA:EE_|CH0PR12MB8461:EE_ X-MS-Office365-Filtering-Correlation-Id: d2264491-cc8c-460a-a1da-08dca4f3938a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2024 17:28:43.7705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2264491-cc8c-460a-a1da-08dca4f3938a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8461 From: Alejandro Lucero This is a second version for adding CXL Type2 support with changes from the first RFC patchset. I have removed the introduction about the concerns with BIOS/UEFI after the discussion leading to confirm the need of the functionality implemented, at least is some scenarios. There are two main changes from the RFC: 1) Following concerns about drivers using CXL core without restrictions, the CXL struct to work with is opaque to those drivers, therefore functions are implemented for modifying or reading those structs indirectly. 2) The driver for using the added functionality is not a test driver but a real one: the SFC ethernet network driver. It uses the CXL region mapped for PIO buffers instead of regions inside PCIe BARs. Current CXL kernel code is focused on supporting Type3 CXL devices, aka memory expanders. Type2 CXL devices, aka device accelerators, share some functionalities but require some special handling. First of all, Type2 are by definition specific to drivers doing something and not just a memory expander, so it is expected to work with the CXL specifics. This implies the CXL setup needs to be done by such a driver instead of by a generic CXL PCI driver as for memory expanders. Most of such setup needs to use current CXL core code and therefore needs to be accessible to those vendor drivers. This is accomplished exporting opaque CXL structs and adding and exporting functions for working with those structs indirectly. Some of the patches are based on a patchset sent by Dan Williams [1] which was just partially integrated, most related to making things ready for Type2 but none related to specific Type2 support. Those patches based on Dan´s work have Dan´s signing as co-developer, and a link to the original patch. A final note about CXL.cache is needed. This patchset does not cover it at all, although the emulated Type2 device advertises it. From the kernel point of view supporting CXL.cache will imply to be sure the CXL path supports what the Type2 device needs. A device accelerator will likely be connected to a Root Switch, but other configurations can not be discarded. Therefore the kernel will need to check not just HPA, DPA, interleave and granularity, but also the available CXL.cache support and resources in each switch in the CXL path to the Type2 device. I expect to contribute to this support in the following months, and it would be good to discuss about it when possible. [1] https://lore.kernel.org/linux-cxl/98b1f61a-e6c2-71d4-c368-50d958501b0c@intel.com/T/ Alejandro Lucero (15): cxl: add type2 device basic support cxl: add function for type2 cxl regs setup cxl: add function for type2 resource request cxl: add capabilities field to cxl_dev_state cxl: fix use of resource_contains cxl: add function for setting media ready by an accelerator cxl: support type2 memdev creation cxl: indicate probe deferral cxl: define a driver interface for HPA free space enumaration cxl: define a driver interface for DPA allocation cxl: make region type based on endpoint type cxl: allow region creation by type2 drivers cxl: preclude device memory to be used for dax cxl: add function for obtaining params from a region efx: support pio mapping based on cxl drivers/cxl/core/cdat.c | 3 + drivers/cxl/core/core.h | 1 + drivers/cxl/core/hdm.c | 160 +++++++-- drivers/cxl/core/mbox.c | 1 + drivers/cxl/core/memdev.c | 122 +++++++ drivers/cxl/core/port.c | 4 +- drivers/cxl/core/region.c | 459 ++++++++++++++++++++++---- drivers/cxl/core/regs.c | 11 +- drivers/cxl/cxl.h | 9 +- drivers/cxl/cxlmem.h | 11 + drivers/cxl/mem.c | 24 +- drivers/cxl/pci.c | 39 ++- drivers/net/ethernet/sfc/Makefile | 2 +- drivers/net/ethernet/sfc/ef10.c | 25 +- drivers/net/ethernet/sfc/efx.c | 6 + drivers/net/ethernet/sfc/efx_cxl.c | 134 ++++++++ drivers/net/ethernet/sfc/efx_cxl.h | 30 ++ drivers/net/ethernet/sfc/mcdi_pcol.h | 3 + drivers/net/ethernet/sfc/net_driver.h | 4 + drivers/net/ethernet/sfc/nic.h | 1 + include/linux/cxl_accel_mem.h | 58 ++++ include/linux/cxl_accel_pci.h | 23 ++ 22 files changed, 1021 insertions(+), 109 deletions(-) create mode 100644 drivers/net/ethernet/sfc/efx_cxl.c create mode 100644 drivers/net/ethernet/sfc/efx_cxl.h create mode 100644 include/linux/cxl_accel_mem.h create mode 100644 include/linux/cxl_accel_pci.h