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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Date: Tue, 7 Jan 2025 15:09:46 +0100 Message-ID: <20250107141015.3367194-1-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE9:EE_|CY5PR12MB6574:EE_ X-MS-Office365-Filtering-Correlation-Id: 269a3047-9d9e-4f21-d344-08dd2f25115e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?xN3AWOYZc8UQAU9ifpYG06k3r43d794?= =?utf-8?q?yng/e1XSWfUJ6Ua73df2PJ3ciEi8EDo8/aGCJIsrUDUAgdp023C9XDt3tIrWQFQzX?= =?utf-8?q?F8QvAiLKlepBhkdjnlsgx+Hu4TM0RrXVRDuwpj/CoOtOZz9JA/C1Hr+Vy1BGPQjji?= =?utf-8?q?boFRgu6RwFpmT/9S/Lnjn0bqRzmsTdBizoeG0A0oiQHOiJzoITrSNAcZ+jJ+SRA16?= =?utf-8?q?bPwL+z89VfhWoKbrCDr+qHrBy926nVhy8WMgcrPZfxGu4hvU3MFr/Fa/pyHKWohP0?= =?utf-8?q?q36C58/1SoWHEE35azb/bgJhyICz8CbOvzHJEeCfFy5gP1e+BoodiQY65/5uLh2kw?= =?utf-8?q?/My60daI8UCpuqUoFMhTbljdWE+LkbScbVdZo4fG9UuzkxN40dDQ7yTwFZDsXAYju?= =?utf-8?q?xF5HSi/j9uoH5hG3aMatUPCMPvJbPQs93DiFuGke6CPYqykd/Ob5+I2o0Jgb2KGqZ?= =?utf-8?q?B+gAFi28sA+Zshf2fZciE9JQd02Xqsu6XBkpgD3wJMvAjrNXFQ/w0pQjk8+xvDbv6?= =?utf-8?q?Z6lMiKrtONCm/HvQ/L61z98FX8r1S7GOy3jgR0INxm599Q3YT56qN6u3QHIUZOhno?= =?utf-8?q?nkkG8xajIGXgEHLRYFtpCEp+wLMOuSFPI4/s/BF6ElORg49/p/req4ZcUAiZjslnM?= =?utf-8?q?mMHfu+pNPKzHWEbPl79LZI8HPGx7doltWtiXYT3n+Xk2QJ0SLbnofqm6vkJ1S5v2O?= =?utf-8?q?NaYcFRKgD0Y9BR5j6iHvSiGlq5OUziWajV34KcQnbUCxpu4FJRv3FzxbDHpj8msyA?= =?utf-8?q?ny4/QAHgXb3qQN3HFjx6KZSLGl6Kn7sLw0XeeZ96+Y6axJotLlc4yR/fT51PurWeF?= =?utf-8?q?HfAt+opDZpEWyVElPYxnfejAwMKK75R0HaWMp6Whfu0hORh7tuQgRz0o81UdrxODP?= =?utf-8?q?QNwWcvOM0F64/2Jf/B5I3bzWYvccG/mRg8Bs6PiiTrTFNAQy08exFH2vgQodUw8us?= =?utf-8?q?aq4Aj83ivK5gvdZkjEdIbB5KQfIv6//xao8n6cNKqpROPvLvJ8poOzAWeGufJEclZ?= =?utf-8?q?rUPlRvp8RwtX9gxwkUn0nEg3HN2vftU6YJTT1z+A4Rak9rSy/q1npkoScVY5cB48A?= =?utf-8?q?T72z5/e3H7pQdzuWeFvf1MxksCoQ/kIdGHiyeFrkmvhTGSEAW9GunWQiuUgdnMbvm?= =?utf-8?q?Kkx3PDUg03EnzqZQBwhCmYJO2URvwMnQr1cfcnhLoWRrOtT+G0zxMz82FFBz8umBH?= =?utf-8?q?8J7OA2xkQdz8eeNDBGw4Znbnlz5AzDfGicwR6nwIn4H1xLMYuyJtmuZn3sMAWw9tN?= =?utf-8?q?N+IdlQWwStkAqEgH7UVmxeGKruxxfB2jVzxI7Vshb3B99pQPOLsP+9YFM4Y/QWUrw?= =?utf-8?q?s9kp5DngZr/wFXz5YlElxgl3iqw7EBegMhM/0s9XIau5snps7hdvAw0FvGNAhJ+2J?= =?utf-8?q?s44nqbbz0xDqEFbQcRHzSV0cZNabryUlMTfA75pZU8Gu3KD+8DbzAg=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2025 14:10:40.6638 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 269a3047-9d9e-4f21-d344-08dd2f25115e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6574 This patch set adds support of address translation and enables this for AMD Zen5 platforms. This is a new appoach in response to an earlier attempt to implement CXL address translation [1] and the comments on it, esp. Dan's [2]. Dan suggested to solve this by walking the port hierarchy from the host port to the host bridge. When crossing memory domains from one port to the other, HPA translations are applied using a callback function to handle platform specifics. The CXL driver currently does not implement address translation which assumes the host physical addresses (HPA) and system physical addresses (SPA) are equal. Systems with different HPA and SPA addresses need address translation. If this is the case, the hardware addresses esp. used in the HDM decoder configurations are different to the system's or parent port address ranges. E.g. AMD Zen5 systems may be configured to use 'Normalized addresses'. Then, CXL endpoints have their own physical address base which is not the same as the SPA used by the CXL host bridge. Thus, addresses need to be translated from the endpoint's to its CXL host bridge's address range. To enable address translation, the endpoint's HPA range must be translated to each of the parent port's address ranges up to the root decoder. This is implemented by traversing the decoder and port hierarchy from the endpoint up to the root port and applying platform specific translation functions to determine the next HPA range of the parent port where needed: if (cxl_port->to_hpa) hpa = cxl_port->to_hpa(cxl_decoder, hpa) A callback is introduced to translate an HPA range from a port to its parent. The root port's HPA range is equivalent to the system's SPA range and can then be used to find an endpoint's root port and region. Also, translated HPA ranges must be used to calculate the endpoint position in the region. Once the region was found, the decoders of all ports between the endpoint and the root port need to be found based on the translated HPA. Configuration checks and interleaving setup must be modified as necessary to support address translation. Note that only auto-discovery of decoders is supported. Thus, decoders are locked and cannot be configured manually. Finally, Zen5 address translation is enabled using ACPI PRMT. Purpose of patches: * Patches #1-#4: Minor cleanups and updates separated from the actual implementation * Patches #5-#12, #14, #17, #18: Code rework and refactoring. * Patches #13, #15, #16, #19-#24: Functional changes for address translation (common code). * Patch #25, #26: AMD Zen5 address translation. * Patch #27-#29: Changes to improve debug messages for better debugging. [1] https://lore.kernel.org/linux-cxl/20240701174754.967954-1-rrichter@amd.com/ [2] https://lore.kernel.org/linux-cxl/669086821f136_5fffa29473@dwillia2-xfh.jf.intel.com.notmuch/ Robert Richter (29): cxl: Remove else after return cxl/pci: Moving code in cxl_hdm_decode_init() cxl/pci: cxl_hdm_decode_init: Move comment cxl/pci: Add comments to cxl_hdm_decode_init() cxl/region: Move find_cxl_root() to cxl_add_to_region() cxl/region: Factor out code to find the root decoder cxl/region: Factor out code to find a root decoder's region cxl/region: Split region registration into an initialization and adding part cxl/region: Use iterator to find the root port in cxl_find_root_decoder() cxl/region: Add function to find a port's switch decoder by range cxl/region: Unfold cxl_find_root_decoder() into cxl_endpoint_initialize() cxl: Modify address translation callback for generic use cxl: Introduce callback to translate an HPA range from a port to its parent cxl: Introduce parent_port_of() helper cxl/region: Use an endpoint's SPA range to find a region cxl/region: Use translated HPA ranges to calculate the endpoint position cxl/region: Rename function to cxl_find_decoder_early() cxl/region: Avoid duplicate call of cxl_find_decoder_early() cxl/region: Use endpoint's HPA range to find the port's decoder cxl/region: Use translated HPA ranges to find the port's decoder cxl/region: Lock decoders that need address translation cxl/region: Use translated HPA ranges to create a region cxl/region: Use root decoders interleaving parameters to create a region cxl/region: Use endpoint's SPA range to check a region cxl/amd: Enable Zen5 address translation using ACPI PRMT MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) cxl/region: Show message on registration failure cxl/region: Show message on broken target list cxl: Show message when a decoder was added to a port MAINTAINERS | 7 + drivers/cxl/Kconfig | 4 + drivers/cxl/acpi.c | 14 +- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/amd.c | 227 +++++++++++++++++++++ drivers/cxl/core/cdat.c | 2 +- drivers/cxl/core/core.h | 6 + drivers/cxl/core/hdm.c | 3 +- drivers/cxl/core/pci.c | 44 +++-- drivers/cxl/core/port.c | 22 ++- drivers/cxl/core/region.c | 407 ++++++++++++++++++++++++++++---------- drivers/cxl/cxl.h | 16 +- drivers/cxl/port.c | 22 +-- 13 files changed, 623 insertions(+), 152 deletions(-) create mode 100644 drivers/cxl/core/amd.c base-commit: 2f84d072bdcb7d6ec66cc4d0de9f37a3dc394cd2