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[0/4] cxl: Delay HB port and switch dport probing until endpoint dev probe

Message ID 20250404230049.3578835-1-dave.jiang@intel.com
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Series cxl: Delay HB port and switch dport probing until endpoint dev probe | expand

Message

Dave Jiang April 4, 2025, 10:57 p.m. UTC 
This series attempts to delay the setup of dports and Host Bridge (HB) register
probing until when the endpoint device (memdev) is being probed. At this point,
the CXL link is established and all the devices along the CXL link path up to
the Root Port (RP) should be active.

And hopefully this help a bit with Robert's issue raised in the "Inactive
downstream port handling" series [1]. Testing would be appreicated. Thank you!

[1]: https://lore.kernel.org/linux-cxl/67c8a0cc23ec_24b64294f6@dwillia2-xfh.jf.intel.com.notmuch/

---
Dave Jiang (4):
      cxl: Saperate out CXL dport->id vs actual dport hardware id
      cxl: Defer hardware dport->port_id assignment and registers probing
      cxl: Add late host bridge uport mapping update
      cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions

 drivers/cxl/acpi.c            |  17 +++++-
 drivers/cxl/core/core.h       |   4 ++
 drivers/cxl/core/hdm.c        |  51 ++++++++++++++---
 drivers/cxl/core/pci.c        |  74 +++++++++++++++++++++----
 drivers/cxl/core/port.c       | 186 ++++++++++++++++++++++++++++++++++++++++++++++----------------
 drivers/cxl/cxl.h             |  25 +++++++++
 drivers/cxl/port.c            |  21 +------
 tools/testing/cxl/Kbuild      |   3 -
 tools/testing/cxl/test/mock.c |  34 ++++++++----
 9 files changed, 315 insertions(+), 100 deletions(-)      

base-commit: a0ba0d4ec5e79ce96317a057ce4a60d8aaf0af6e