Show patches with: Submitter = Dave Jiang       |    State = Action Required       |   171 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v7,07/11] cxl: Add helper function that calculate performance data for downstream ports cxl: Add support for QTG ID retrieval for CXL subsystem - 1 - --- 2023-06-16 Dave Jiang New
[v7,06/11] cxl: Store the access coordinates for the generic ports cxl: Add support for QTG ID retrieval for CXL subsystem - 1 - --- 2023-06-16 Dave Jiang New
[v7,05/11] cxl: Calculate and store PCI link latency for the downstream ports cxl: Add support for QTG ID retrieval for CXL subsystem - 1 - --- 2023-06-16 Dave Jiang New
[v7,04/11] cxl: Add support for _DSM Function for retrieving QTG ID cxl: Add support for QTG ID retrieval for CXL subsystem - 1 - --- 2023-06-16 Dave Jiang New
[v7,03/11] cxl: Add callback to parse the SSLBIS subtable from CDAT cxl: Add support for QTG ID retrieval for CXL subsystem - 1 - --- 2023-06-16 Dave Jiang New
[v7,02/11] cxl: Add callback to parse the DSLBIS subtable from CDAT cxl: Add support for QTG ID retrieval for CXL subsystem - 1 - --- 2023-06-16 Dave Jiang New
[v7,01/11] cxl: Add callback to parse the DSMAS subtables from CDAT cxl: Add support for QTG ID retrieval for CXL subsystem - 1 - --- 2023-06-16 Dave Jiang New
[v4,4/4] acpi: Add defines for CDAT SSLBIS acpi: Add CDAT parsing support to ACPI tables code 1 1 - --- 2023-06-14 Dave Jiang New
[v4,2/4] lib/firmware_table: tables: Add CDAT table parsing support acpi: Add CDAT parsing support to ACPI tables code 1 1 - --- 2023-06-14 Dave Jiang New
[v4,1/4] acpi: Move common tables helper functions to common lib acpi: Add CDAT parsing support to ACPI tables code 1 1 - --- 2023-06-14 Dave Jiang New
[v2] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' [v2] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' 1 1 - --- 2023-06-12 Dave Jiang New
[ndctl,v2,3/3] ndctl: cxl: add QoS class check for CXL region creation ndctl: Add support of QoS Throttling Group (QTG) id for CXL CLI - - - --- 2023-05-25 Dave Jiang New
[ndctl,v2,2/3] ndctl: cxl: Add QoS class support for the memory device ndctl: Add support of QoS Throttling Group (QTG) id for CXL CLI - - - --- 2023-05-25 Dave Jiang New
[ndctl,v2,1/3] ndctl: cxl: Add QoS class retrieval for the root decoder ndctl: Add support of QoS Throttling Group (QTG) id for CXL CLI - - - --- 2023-05-25 Dave Jiang New
[v2,4/4] acpi: numa: Add helper function to retrieve the performance attributes acpi: numa: Add target support for generic port to HMAT parsing - 1 - --- 2023-05-19 Dave Jiang New
[v2,3/4] acpi: numa: Add setting of generic port system locality attributes acpi: numa: Add target support for generic port to HMAT parsing - - - --- 2023-05-19 Dave Jiang New
[v2,2/4] acpi: numa: Add genport target allocation to the HMAT parsing acpi: numa: Add target support for generic port to HMAT parsing - 1 - --- 2023-05-19 Dave Jiang New
[v2,1/4] acpi: numa: Create enum for memory_target access coordinates indexing acpi: numa: Add target support for generic port to HMAT parsing - 1 - --- 2023-05-19 Dave Jiang New
[v4,2/2] cxl: Move cxl_await_media_ready() to before capacity info retrieval Untitled series #749058 - 1 - --- 2023-05-18 Dave Jiang New
[v3,2/2] cxl: Move cxl_await_media_ready() to before capacity info retrieval cxl: Move operations after memory is ready - 1 - --- 2023-05-18 Dave Jiang New
[v2,2/2] cxl: Move cxl_await_media_ready() to before capacity info retrieval ] cxl: Move operations after memory is ready - 1 - --- 2023-05-18 Dave Jiang New
[v2,1/2] cxl: Wait Memory_Info_Valid before access memory related info ] cxl: Move operations after memory is ready - 1 - --- 2023-05-18 Dave Jiang New
[v3] cxl: Add checksum verification to CDAT from CXL [v3] cxl: Add checksum verification to CDAT from CXL - 3 - --- 2023-05-12 Dave Jiang New
[v2,4/4] cxl: Add support for reading CXL switch CDAT table cxl: Prep for QoS class support - 3 - --- 2023-05-11 Dave Jiang New
[v2,3/4] cxl: Add checksum verification to CDAT from CXL cxl: Prep for QoS class support - 2 - --- 2023-05-11 Dave Jiang New
[v2,1/4] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute cxl: Prep for QoS class support - 3 - --- 2023-05-11 Dave Jiang New
[RESEND,v2] cxl: Warn of flexible array in struct cxl_root_decoder [RESEND,v2] cxl: Warn of flexible array in struct cxl_root_decoder - 3 - --- 2023-04-27 Dave Jiang New
cxl: Add warning comment to cxl_root_decoder cxl: Add warning comment to cxl_root_decoder - - - --- 2023-04-26 Dave Jiang New
hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS - - - --- 2023-03-22 Dave Jiang New
cxl: fix compile warning for cxl_security_ops extern cxl: fix compile warning for cxl_security_ops extern - 1 2 --- 2023-03-01 Dave Jiang New
[RFC] hw/acpi: Add support for Generic Port Affinity Structure to SRAT [RFC] hw/acpi: Add support for Generic Port Affinity Structure to SRAT - - - --- 2023-02-27 Dave Jiang New
[v9] cxl: add RAS status unmasking for CXL [v9] cxl: add RAS status unmasking for CXL 1 2 - --- 2023-02-21 Dave Jiang New
[v4,5/7] cxl: create emulated cxl_hdm for devices that do not have HDM decoders cxl: Introduce HDM decoder emulation from DVSEC range registers - 1 - --- 2023-02-08 Dave Jiang New
[v4,4/7] cxl: emulate HDM decoder from DVSEC range registers cxl: Introduce HDM decoder emulation from DVSEC range registers - 1 - --- 2023-02-08 Dave Jiang New
[v4,3/7] cxl: refactor cxl_hdm_decode_init() cxl: Introduce HDM decoder emulation from DVSEC range registers - 1 - --- 2023-02-08 Dave Jiang New
[v4,2/7] cxl: export cxl_dvsec_rr_decode() to cxl_port cxl: Introduce HDM decoder emulation from DVSEC range registers - 1 - --- 2023-02-08 Dave Jiang New
[v4,1/7] cxl: break out range register decoding from cxl_hdm_decode_init() cxl: Introduce HDM decoder emulation from DVSEC range registers - 1 - --- 2023-02-08 Dave Jiang New
hw/cxl: Add QTG _DSM support for ACPI0017 device hw/cxl: Add QTG _DSM support for ACPI0017 device - - - --- 2023-01-26 Dave Jiang New
cxl: change 'cxl_nvb' naming to 'nv_bridge' to improve readability cxl: change 'cxl_nvb' naming to 'nv_bridge' to improve readability - 2 - --- 2023-01-25 Dave Jiang New
cxl: fix cdat_available state post error cxl: fix cdat_available state post error - - - --- 2023-01-13 Dave Jiang New
[ndctl,v3,1/4] ndctl: add CXL bus detection [ndctl,v3,1/4] ndctl: add CXL bus detection - 2 - --- 2022-12-16 Dave Jiang New
[ndctl,v2,1/4] ndctl: add CXL bus detection ndctl: Add security test for cxl devices through nvdimm - 1 - --- 2022-12-14 Dave Jiang New
[ndctl,v2] ndctl: create disable master passphrase support [ndctl,v2] ndctl: create disable master passphrase support - - - --- 2022-12-08 Dave Jiang New
[v5,11/11] cxl/pci: Add callback to log AER correctable error Untitled series #700613 - 1 - --- 2022-11-30 Dave Jiang New
[v7,20/20] cxl: add dimm_id support for __nvdimm_create() Introduce security commands for CXL pmem device - 1 - --- 2022-11-30 Dave Jiang New
[v7,19/20] acpi/nfit: bypass cpu_cache_invalidate_memregion() when in test config Introduce security commands for CXL pmem device - 1 - --- 2022-11-30 Dave Jiang New
[v7,18/20] cxl: bypass cpu_cache_invalidate_memregion() when in test config Introduce security commands for CXL pmem device - 1 - --- 2022-11-30 Dave Jiang New
[v4,11/11] cxl/pci: Add callback to log AER correctable error cxl/pci: Add fundamental error handling - 1 - --- 2022-11-29 Dave Jiang New
[v4,10/11] PCI/AER: Add optional logging callback for correctable error cxl/pci: Add fundamental error handling 1 2 - --- 2022-11-29 Dave Jiang New
[v4,10/10] cxl: add man page documentation for monitor cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,09/10] cxl: add systemd service for monitor cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,08/10] cxl: add an optional pid check to event parsing cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,07/10] cxl: add monitor command to cxl cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,06/10] cxl: add logging functions for monitor cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,05/10] cxl: add monitor function for event trace events cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,04/10] cxl: add common function to disable event trace cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,03/10] cxl: add common function to enable event trace cxl: add monitor support for trace events - - - --- 2022-11-08 Dave Jiang New
[v4,02/10] cxl: add helper to parse through all current events cxl: add monitor support for trace events - - 1 --- 2022-11-08 Dave Jiang New
[v4,01/10] cxl: add helper function to parse trace event to json object cxl: add monitor support for trace events - - 1 --- 2022-11-08 Dave Jiang New
cxl: update eiw_to_ways() comment referring to cxl spec cxl: update eiw_to_ways() comment referring to cxl spec - 1 - --- 2022-10-24 Dave Jiang New
[v3] cxl: check decoder count for end device [v3] cxl: check decoder count for end device - 1 - --- 2022-10-24 Dave Jiang New
cxl: update var names for interleave ways conversion macros cxl: update var names for interleave ways conversion macros - - - --- 2022-10-11 Dave Jiang New
cxl: update var names for interleave granularity conversion macros cxl: update var names for interleave granularity conversion macros - 1 - --- 2022-10-11 Dave Jiang New
[v5,6/6] cxl: export intereleave capability as port sysfs attribute Add sanity check for interleave setup - 1 - --- 2022-08-25 Dave Jiang djbw Under Review
[v5,5/6] cxl: export interleave address mask as port sysfs attribute Add sanity check for interleave setup - 1 - --- 2022-08-25 Dave Jiang djbw Under Review
[v5,4/6] cxl: change cxl_port_attribute_groups naming to avoid confusion Add sanity check for interleave setup - 1 - --- 2022-08-25 Dave Jiang djbw Under Review
[v5,3/6] tools/testing/cxl: Add interleave check support to mock cxl port device Add sanity check for interleave setup - 2 - --- 2022-08-25 Dave Jiang djbw Under Review
[v5,2/6] cxl: Add CXL spec v3.0 interleave support Add sanity check for interleave setup - 2 - --- 2022-08-25 Dave Jiang djbw Under Review
[v5,1/6] cxl: Add check for result of interleave ways plus granularity combo Add sanity check for interleave setup - 2 - --- 2022-08-25 Dave Jiang djbw Under Review
[2/2] cxl: export intereleave capability as port sysfs attribute [1/2] cxl: export interleave address mask as port sysfs attribute - - - --- 2022-08-16 Dave Jiang djbw Under Review
[1/2] cxl: export interleave address mask as port sysfs attribute [1/2] cxl: export interleave address mask as port sysfs attribute - - - --- 2022-08-16 Dave Jiang djbw Under Review
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