Show patches with: Submitter = Bowman, Terry       |    Archived = No       |   178 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v6,17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,14/27] cxl/pci: Early setup RCH dport component registers from RCRB cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,13/27] cxl/mem: Prepare for early RCH dport component register setup cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,12/27] cxl/regs: Remove early capability checks in Component Register setup cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,11/27] cxl/port: Remove Component Register base address from struct cxl_dport cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,08/27] cxl/pci: Refactor component register discovery for reuse cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,07/27] cxl/core/regs: Add @dev to cxl_register_map cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,06/27] cxl: Rename 'uport' to 'uport_dev' cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,03/27] cxl: Updates for CXL Test to work with RCH cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-22 Bowman, Terry Superseded
[v6,02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-06-22 Bowman, Terry Superseded
[v6,01/27] cxl/port: Fix NULL pointer access in devm_cxl_add_port() cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-22 Bowman, Terry Superseded
[v5,26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling cxl/pci: Add support for RCH RAS error handling 1 - - --- 2023-06-07 Bowman, Terry Superseded
[v5,25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler cxl/pci: Add support for RCH RAS error handling 1 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,24/26] cxl/pci: Add RCH downstream port error logging cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,23/26] cxl/pci: Disable root port interrupts in RCH mode cxl/pci: Add support for RCH RAS error handling - - - --- 2023-06-07 Bowman, Terry Superseded
[v5,22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors cxl/pci: Add support for RCH RAS error handling - - - --- 2023-06-07 Bowman, Terry Superseded
[v5,21/26] cxl/pci: Update CXL error logging to use RAS register address cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module cxl/pci: Add support for RCH RAS error handling 1 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,19/26] cxl/pci: Add RCH downstream port AER register discovery cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,17/26] cxl/port: Remove Component Register base address from struct cxl_dport cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,16/26] cxl/port: Remove Component Register base address from struct cxl_port cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port cxl/pci: Add support for RCH RAS error handling - - - --- 2023-06-07 Bowman, Terry Superseded
[v5,11/26] cxl/pci: Early setup RCH dport component registers from RCRB cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,10/26] cxl/mem: Prepare for early RCH dport component register setup cxl/pci: Add support for RCH RAS error handling - - - --- 2023-06-07 Bowman, Terry Superseded
[v5,09/26] cxl/regs: Remove early capability checks in Component Register setup cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,07/26] cxl/acpi: Moving add_host_bridge_uport() around cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,06/26] cxl/pci: Refactor component register discovery for reuse cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,05/26] cxl/core/regs: Add @dev to cxl_register_map cxl/pci: Add support for RCH RAS error handling - - - --- 2023-06-07 Bowman, Terry Superseded
[v5,04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() cxl/pci: Add support for RCH RAS error handling - - - --- 2023-06-07 Bowman, Terry Superseded
[v5,03/26] cxl: Rename member @dport of struct cxl_dport to @dev cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v5,02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability cxl/pci: Add support for RCH RAS error handling - - - --- 2023-06-07 Bowman, Terry Superseded
[v5,01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-06-07 Bowman, Terry Superseded
[v4,23/23] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling cxl/pci: Add support for RCH RAS error handling - - - --- 2023-05-23 Bowman, Terry Superseded
[v4,22/23] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler cxl/pci: Add support for RCH RAS error handling 1 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,21/23] cxl/pci: Add RCH downstream port error logging cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,20/23] cxl/pci: Prepare for logging RCH downstream port protocol errors cxl/pci: Add support for RCH RAS error handling - - - --- 2023-05-23 Bowman, Terry Superseded
[v4,19/23] cxl/pci: Update CXL error logging to use RAS register address cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,18/23] PCI/AER: Refactor cper_print_aer() for use by CXL driver module cxl/pci: Add support for RCH RAS error handling 1 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,17/23] cxl/pci: Add RCH downstream port AER register discovery cxl/pci: Add support for RCH RAS error handling - 2 - --- 2023-05-23 Bowman, Terry Superseded
[v4,16/23] cxl/pci: Remove Component Register base address from struct cxl_dev_state cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,15/23] cxl/port: Remove Component Register base address from struct cxl_dport cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,14/23] cxl/port: Remove Component Register base address from struct cxl_port cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,13/23] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,12/23] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,11/23] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,10/23] cxl/port: Store the port's Component Register mappings in struct cxl_port cxl/pci: Add support for RCH RAS error handling - - - --- 2023-05-23 Bowman, Terry Superseded
[v4,09/23] cxl/pci: Early setup RCH dport component registers from RCRB cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,08/23] cxl/regs: Remove early capability checks in Component Register setup cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,07/23] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,06/23] cxl/acpi: Moving add_host_bridge_uport() around cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,05/23] cxl/pci: Refactor component register discovery for reuse cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,04/23] cxl/core/regs: Add @dev to cxl_register_map cxl/pci: Add support for RCH RAS error handling - - - --- 2023-05-23 Bowman, Terry Superseded
[v4,03/23] cxl: Rename member @dport of struct cxl_dport to @dev cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v4,02/23] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability cxl/pci: Add support for RCH RAS error handling - - - --- 2023-05-23 Bowman, Terry Superseded
[v4,01/23] cxl/acpi: Probe RCRB later during RCH downstream port creation cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-05-23 Bowman, Terry Superseded
[v3,6/6] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling cxl/pci: Add support for RCH RAS error handling - - - --- 2023-04-11 Bowman, Terry Superseded
[v3,5/6] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler cxl/pci: Add support for RCH RAS error handling - - - --- 2023-04-11 Bowman, Terry Superseded
[v3,4/6] cxl/pci: Add RCH downstream port error logging cxl/pci: Add support for RCH RAS error handling - - - --- 2023-04-11 Bowman, Terry Superseded
[v3,3/6] PCI/AER: Export cper_print_aer() for use by modules cxl/pci: Add support for RCH RAS error handling - 1 - --- 2023-04-11 Bowman, Terry Superseded
[v3,2/6] efi/cper: Export cper_mem_err_unpack() for use by modules cxl/pci: Add support for RCH RAS error handling 1 - - --- 2023-04-11 Bowman, Terry Superseded
[v3,1/6] cxl/pci: Add RCH downstream port AER and RAS register discovery cxl/pci: Add support for RCH RAS error handling - - - --- 2023-04-11 Bowman, Terry Superseded
[v2,5/5] cxl/pci: Add RCH downstream port error logging cxl/pci: Add support for RCH RAS error handling - - - --- 2023-03-23 Bowman, Terry Superseded
[v2,4/5] cxl/pci: Forward RCH downstream port-detected errors to the CXL.mem dev handler cxl/pci: Add support for RCH RAS error handling - - - --- 2023-03-23 Bowman, Terry Superseded
[v2,3/5] pci/aer: Export cper_print_aer() for CXL driver logging cxl/pci: Add support for RCH RAS error handling 1 1 - --- 2023-03-23 Bowman, Terry Superseded
[v2,2/5] efi/cper: Export cper_mem_err_unpack() for CXL logging cxl/pci: Add support for RCH RAS error handling - - - --- 2023-03-23 Bowman, Terry Superseded
[v2,1/5] cxl/pci: Add RCH downstream port AER and RAS register discovery cxl/pci: Add support for RCH RAS error handling - - - --- 2023-03-23 Bowman, Terry Superseded
[1/5] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support cxl: Log downport PCIe AER and CXL RAS error information - - - --- 2022-10-21 Bowman, Terry Accepted
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