| Message ID | 164375309615.513620.7874131241128599893.stgit@dwillia2-desk3.amr.corp.intel.com |
|---|---|
| State | Accepted |
| Commit | 06e279e5ebe4f32ffe544ec96a199870319a7315 |
| Headers | show |
| Series | None | expand |
On Tue, 01 Feb 2022 14:06:32 -0800 Dan Williams <dan.j.williams@intel.com> wrote: > From: Ben Widawsky <ben.widawsky@intel.com> > > The PCIe device DVSEC, defined in the CXL 2.0 spec, 8.1.3 is required to > be implemented by CXL 2.0 endpoint devices. In preparation for consuming > this information in a new cxl_mem driver, retrieve the CXL DVSEC > position and warn about the implications of not finding it. Allow for > mailbox operation even if the CXL DVSEC is missing. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > Changes since v3: > - Move the s/device_dvsec/cxl_dvsec/ rename one patch sooner (Jonathan) > - Warn, don't fail, when CXL DVSEC not found > > drivers/cxl/cxlmem.h | 2 ++ > drivers/cxl/pci.c | 6 ++++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index 90d67fff5bed..5cf5329e13a9 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -98,6 +98,7 @@ struct cxl_mbox_cmd { > * > * @dev: The device associated with this CXL state > * @regs: Parsed register blocks > + * @cxl_dvsec: Offset to the PCIe device DVSEC > * @payload_size: Size of space for payload > * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) > * @lsa_size: Size of Label Storage Area > @@ -126,6 +127,7 @@ struct cxl_dev_state { > struct device *dev; > > struct cxl_regs regs; > + int cxl_dvsec; > > size_t payload_size; > size_t lsa_size; > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index bf14c365ea33..c94002166084 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -408,6 +408,12 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > if (IS_ERR(cxlds)) > return PTR_ERR(cxlds); > > + cxlds->cxl_dvsec = pci_find_dvsec_capability( > + pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); > + if (!cxlds->cxl_dvsec) > + dev_warn(&pdev->dev, > + "Device DVSEC not present, skip CXL.mem init\n"); > + > rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); > if (rc) > return rc; >
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 90d67fff5bed..5cf5329e13a9 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -98,6 +98,7 @@ struct cxl_mbox_cmd { * * @dev: The device associated with this CXL state * @regs: Parsed register blocks + * @cxl_dvsec: Offset to the PCIe device DVSEC * @payload_size: Size of space for payload * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) * @lsa_size: Size of Label Storage Area @@ -126,6 +127,7 @@ struct cxl_dev_state { struct device *dev; struct cxl_regs regs; + int cxl_dvsec; size_t payload_size; size_t lsa_size; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bf14c365ea33..c94002166084 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -408,6 +408,12 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (IS_ERR(cxlds)) return PTR_ERR(cxlds); + cxlds->cxl_dvsec = pci_find_dvsec_capability( + pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + if (!cxlds->cxl_dvsec) + dev_warn(&pdev->dev, + "Device DVSEC not present, skip CXL.mem init\n"); + rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); if (rc) return rc;