| Message ID | 165951146924.967013.13625127756930271590.stgit@dwillia2-xfh.jf.intel.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | cxl/region: Endpoint decoder fixes | expand |
On Wed, 03 Aug 2022 00:24:29 -0700 Dan Williams <dan.j.williams@intel.com> wrote: > A recent bug fix added the setup of the endpoint decoder interleave > geometry settings to cxl_region_attach(). Move the HPA setup there as > well to keep all endpoint decoder parameter setting in a central > location. > > Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Signed-off-by: Dan Williams <dan.j.williams@intel.com> Makes sense to me plus works for the random test I hit it with. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/core/hdm.c | 17 ++--------------- > drivers/cxl/core/region.c | 4 ++++ > 2 files changed, 6 insertions(+), 15 deletions(-) > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 8143e2615957..5aadefd670d1 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -499,20 +499,6 @@ static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl) > CXL_HDM_DECODER0_CTRL_TYPE); > } > > -static void cxld_set_hpa(struct cxl_decoder *cxld, u64 *base, u64 *size) > -{ > - struct cxl_region *cxlr = cxld->region; > - struct cxl_region_params *p = &cxlr->params; > - > - cxld->hpa_range = (struct range) { > - .start = p->res->start, > - .end = p->res->end, > - }; > - > - *base = p->res->start; > - *size = resource_size(p->res); > -} > - > static void cxld_clear_hpa(struct cxl_decoder *cxld) > { > cxld->hpa_range = (struct range) { > @@ -601,7 +587,8 @@ static int cxl_decoder_commit(struct cxl_decoder *cxld) > ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id)); > cxld_set_interleave(cxld, &ctrl); > cxld_set_type(cxld, &ctrl); > - cxld_set_hpa(cxld, &base, &size); > + base = cxld->hpa_range.start; > + size = range_len(&cxld->hpa_range); > > writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id)); > writel(lower_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id)); > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index 8e6ff3f39755..a073f16355ca 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -1296,6 +1296,10 @@ static int cxl_region_attach(struct cxl_region *cxlr, > > cxled->cxld.interleave_ways = p->interleave_ways; > cxled->cxld.interleave_granularity = p->interleave_granularity; > + cxled->cxld.hpa_range = (struct range) { > + .start = p->res->start, > + .end = p->res->end, > + }; > > return 0; > >
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 8143e2615957..5aadefd670d1 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -499,20 +499,6 @@ static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl) CXL_HDM_DECODER0_CTRL_TYPE); } -static void cxld_set_hpa(struct cxl_decoder *cxld, u64 *base, u64 *size) -{ - struct cxl_region *cxlr = cxld->region; - struct cxl_region_params *p = &cxlr->params; - - cxld->hpa_range = (struct range) { - .start = p->res->start, - .end = p->res->end, - }; - - *base = p->res->start; - *size = resource_size(p->res); -} - static void cxld_clear_hpa(struct cxl_decoder *cxld) { cxld->hpa_range = (struct range) { @@ -601,7 +587,8 @@ static int cxl_decoder_commit(struct cxl_decoder *cxld) ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id)); cxld_set_interleave(cxld, &ctrl); cxld_set_type(cxld, &ctrl); - cxld_set_hpa(cxld, &base, &size); + base = cxld->hpa_range.start; + size = range_len(&cxld->hpa_range); writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id)); writel(lower_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id)); diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 8e6ff3f39755..a073f16355ca 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1296,6 +1296,10 @@ static int cxl_region_attach(struct cxl_region *cxlr, cxled->cxld.interleave_ways = p->interleave_ways; cxled->cxld.interleave_granularity = p->interleave_granularity; + cxled->cxld.hpa_range = (struct range) { + .start = p->res->start, + .end = p->res->end, + }; return 0;
A recent bug fix added the setup of the endpoint decoder interleave geometry settings to cxl_region_attach(). Move the HPA setup there as well to keep all endpoint decoder parameter setting in a central location. Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- drivers/cxl/core/hdm.c | 17 ++--------------- drivers/cxl/core/region.c | 4 ++++ 2 files changed, 6 insertions(+), 15 deletions(-)