diff mbox series

[ndctl,5/6] cxl/list: Add 'depth' to port listings

Message ID 165973190022.1528532.6351628365510289908.stgit@dwillia2-xfh.jf.intel.com
State New, archived
Headers show
Series cxl/test: Add more region ABI validation | expand

Commit Message

Dan Williams Aug. 5, 2022, 8:38 p.m. UTC 
Simplify the task of determining how deep a port is in the hierarchy by
just emitting what libcxl already counted. This is useful for validating
interleave math.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 Documentation/cxl/lib/libcxl.txt |    1 +
 cxl/json.c                       |    4 ++++
 cxl/lib/libcxl.c                 |    5 +++++
 cxl/lib/libcxl.sym               |    1 +
 cxl/libcxl.h                     |    1 +
 5 files changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
index 72641699633b..5efa60124111 100644
--- a/Documentation/cxl/lib/libcxl.txt
+++ b/Documentation/cxl/lib/libcxl.txt
@@ -290,6 +290,7 @@  int cxl_port_is_enabled(struct cxl_port *port);
 bool cxl_port_is_root(struct cxl_port *port);
 bool cxl_port_is_switch(struct cxl_port *port);
 bool cxl_port_is_endpoint(struct cxl_port *port);
+int cxl_port_get_depth(struct cxl_port *port);
 bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev);
 int cxl_port_get_nr_dports(struct cxl_port *port);
 ----
diff --git a/cxl/json.c b/cxl/json.c
index 82e3c552cdb1..7aefcadb0795 100644
--- a/cxl/json.c
+++ b/cxl/json.c
@@ -761,6 +761,10 @@  static struct json_object *__util_cxl_port_to_json(struct cxl_port *port,
 	if (jobj)
 		json_object_object_add(jport, "host", jobj);
 
+	jobj = json_object_new_int(cxl_port_get_depth(port));
+	if (jobj)
+		json_object_object_add(jport, "depth", jobj);
+
 	if (!cxl_port_is_enabled(port)) {
 		jobj = json_object_new_string("disabled");
 		if (jobj)
diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
index aec3671b1625..4b78ecc1d115 100644
--- a/cxl/lib/libcxl.c
+++ b/cxl/lib/libcxl.c
@@ -2309,6 +2309,11 @@  CXL_EXPORT bool cxl_port_is_endpoint(struct cxl_port *port)
 	return port->type == CXL_PORT_ENDPOINT;
 }
 
+CXL_EXPORT int cxl_port_get_depth(struct cxl_port *port)
+{
+	return port->depth;
+}
+
 CXL_EXPORT struct cxl_bus *cxl_port_get_bus(struct cxl_port *port)
 {
 	struct cxl_bus *bus;
diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
index 573fcdf532d6..7dc3eee8a63c 100644
--- a/cxl/lib/libcxl.sym
+++ b/cxl/lib/libcxl.sym
@@ -96,6 +96,7 @@  global:
 	cxl_port_get_parent;
 	cxl_port_is_root;
 	cxl_port_is_switch;
+	cxl_port_get_depth;
 	cxl_port_to_bus;
 	cxl_port_is_endpoint;
 	cxl_port_to_endpoint;
diff --git a/cxl/libcxl.h b/cxl/libcxl.h
index 4b5490986a2a..aa0a89d91b30 100644
--- a/cxl/libcxl.h
+++ b/cxl/libcxl.h
@@ -89,6 +89,7 @@  int cxl_port_is_enabled(struct cxl_port *port);
 struct cxl_port *cxl_port_get_parent(struct cxl_port *port);
 bool cxl_port_is_root(struct cxl_port *port);
 bool cxl_port_is_switch(struct cxl_port *port);
+int cxl_port_get_depth(struct cxl_port *port);
 struct cxl_bus *cxl_port_to_bus(struct cxl_port *port);
 bool cxl_port_is_endpoint(struct cxl_port *port);
 struct cxl_endpoint *cxl_port_to_endpoint(struct cxl_port *port);